TechOnline India Header
All Articles Products Courses Papers VirtuaLabs Webinars
Top Search Items
C


Techpaper Spotlight

Wind River
Accelerating the Development of Embedded Linux Devices with JTAG On-Chip Debugging
    Login | Register | Welcome, Guest

Topics
 



Mentor Graphics offers IP platform for FPGA designs
Mentor Graphics has brought out Precise-IP platform as part of its Precision Synthesis product line. The platform includes vendor-independent configurable IP from Mentor Graphics and links to categorized third-party IP from leading vendors.
Mentor Graphics has brought out Precise-IP platform as part of its Precision Synthesis product line. The platform includes vendor-independent configurable IP from Mentor Graphics and links to categorized third-party IP from leading vendors.

The third-party IP was certified by the respective IP vendor for the Precision Synthesis technology.

Participating vendors of the Precise-IP Partner Program are ARC, ARM, Aeroflex Gaisler, CAST, Eureka Technology, Helion, IPextreme, Innovative Logic, and OptNgn.

Precise-IP contains a library of configurable IP for use with the Precision Synthesis solution. A wizard creates frequently-used synthesizable IP based on user parameter settings.

The configuration parameters are then validated by a self-checking GUI to ensure configuration conformance. The IP cores are optimized for best quality of results (QoR) across FPGA families.

A catalog of complex cores — such as processors, interface controllers, and application-specific cores — are provided by leading IP vendors and available for multiple FPGA families.

"Mentor's Precise-IP is a big win for design engineers," stated Gary Smith, principal of Gary Smith EDA, in a statement. "Non-proprietary, commercial IP that is vendor independent gives the FPGA designer the freedom to select the device that delivers the best results."

Precision Synthesis product features a design analysis capability that allows designers to cross-probe between multiple views as well as to perform interactive static timing for "what-if" analyses.

1
 
Latest Webinars
· The Next Generation of Ethernet: How the New IEEE Standards Enable Energy Efficiency and Quality-of-Service
· Simplified Physical Layer Receiver Test of Re-timed Architectures Such as USB 3.0, SATA, SAS, PCIe 2
· How to solve the most common high-speed bus issues in embedded design on a budget
· Early access to ARM Core Technology with Fast Models from ARM
· Latest MIPI Standards: PHY and Protocol Testing Guidance
 
Member Company Spotlight
Xilinx
 

Start Your Spartan-3A FPGA DSP Design Now! Evaluate Free Downloadable Tools Built Just for You.


Member Companies