TechOnline India Header
All Articles Products Courses Papers VirtuaLabs Webinars
Top Search Items
C


Techpaper Spotlight

Wind River
Accelerating the Development of Embedded Linux Devices with JTAG On-Chip Debugging
    Login | Register | Welcome, Guest

Topics
 



TSMC, SVTC collaborate on fast-track chip design
A new industry alliance will seek to speed the introduction of new chip design and manufacturing advances.

PORTLAND, Ore. — A new industry alliance will seek to speed the introduction of new chip design and manufacturing advances.

The Innovation Incubation Alliance is being formed by Taiwan Semiconductor Manufacturing Company Ltd. and SVTC Technologies (San Jose, Calif.). The joint effort builds on an earlier alliance designed to accelerate new ideas in chip design and manufacturing. The new alliance follows the formation of a similar venture earlier this month between TSMC and the Interuniversity Microelectronics Centre (IMEC of Leuven, Belgium).

"Startup companies with new ideas now have a U.S. partner--SVTC--where they can incubate their technology and move it beyond the lab to volume production at TSMC," said SVTC CEO Joseph Bronson.

SVTC Technologies merged with Sematech's Advanced Technology Development Facility in 2007, helping fabless chip companies develop intellectual property for mixed-signal applications, including MEMS, memory, novel transistor materials, logic, biotechnology, image sensors and photovoltaics.

The new alliance with TSMC will focus on "More that Moore" applications, a reference to Moore's Law of exponential processing power. The new applications will not depend on scaling.

SVTC has developed R&D processes that are compatible with TSMC's production processes, allowing customers to develop new MEMS chips at SVTC, then transfer the design to TSMC for production. Other applications include devices incorporating new materials and those using novel new chip structures.

SVTC has both 8- and 12-inch process development capabilities. The partners plan to co-market the services emerging from the alliance.

1
 
Latest Webinars
· The Next Generation of Ethernet: How the New IEEE Standards Enable Energy Efficiency and Quality-of-Service
· Simplified Physical Layer Receiver Test of Re-timed Architectures Such as USB 3.0, SATA, SAS, PCIe 2
· How to solve the most common high-speed bus issues in embedded design on a budget
· Early access to ARM Core Technology with Fast Models from ARM
· Latest MIPI Standards: PHY and Protocol Testing Guidance
 
Member Company Spotlight
Xilinx
 

Start Your Spartan-3A FPGA DSP Design Now! Evaluate Free Downloadable Tools Built Just for You.


Member Companies