PLS Programmierbare Logik & Systeme's Universal Debug Engine (UDE) 2.7 now supports the 32-bit Power Architecture MCUs of the MPC5668x series from Freescale.
The high-end automotive microcontrollers that were designed for use as central body electronics controllers and for automotive gateway applications are clocked at up to 116 MHz and feature an e200z650 core as master and an e200z0 core as slave I/O processor, 2 MB flash and up to 592 KB of SRAM.
The modular architecture of the UDE has full effect when multicore debugging within one user interface. For example, the four code breakpoints and two watchpoints per core, which are supported by on-chip hardware, can be used by the developer direct in the program and watch window of the respective core.
All other on-chip trigger possibilities are also obviously fully supported by the UDE 2.7. In doing so, the debugger independently takes over administration of the on-chip resources.
Connection to dual-core devices is typically carried out via a single JTAG interface. The JTAG extender of the Universal Access Device family (UAD2/UAD3+) from PLS allows a distance of several meters between target and host PC with high immunity to interferences and transfer rates of up to 1 MByte/s. This not only ensures users of the MPC5668x series an extremely fast flash programming and short turn-around times during development, but also the possibility of using the Universal Debug Engine for maintenance and service.
The existing Nexus unit on all the MPC5668x family enables memory access by the debugger during program run-time. This feature can be used, among other things, for real-time visualization of variables and expressions of them to represent measured values.
This enables a virtual input/output interface is implemented via the JTAG debug channel. The UAD2+ with trace option or the UAD3+ enable program trace and data trace via the Nexus interface, whereby in both cases the 12-bit wide trace data port of the MPC5668x series is used. With the UAD3+ up to 4 GB of memory are available for recording.
Each sample can contain eight additional external hardware signals. The recording of the samples takes place synchronously to the Nexus clock frequency. This enables an optimal use of the trace memory and application optimized timestamps.
Start and stop of the recording can be controlled via pre-trigger, mid-trigger, post-trigger or address-trigger. The trace window in the user interface offers the developer a direct link from the trace samples to the associated source code, display of the program run-time on the basis of the timestamps as well as search functions.
The UDE 2.7 also supports variable length encoding (VLE), which is implemented in the core architectures Power e200z650 and Power e200z0. This alternative instruction set, consisting of 16-bit and 32-bit wide instructions, enables a high code density.
Both Freescale’s CodeWarrior for MPC56xx devices and the Power Architecture compilers from Greenhills and WindRiver and the GNU implementation from HighTec EDV-Systeme can be used together with the UDE 2.7.