Digital Core Design, leading Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house from Poland has introduced the world’s most advanced 80C51 architecture. Thanks to the unique combination of instruction set and most of all optimized architecture, Polish company has achieved results which are more than 56 times better than standard 8051 and more than 70% more efficient, than
the nearest competition.
"We’re proud to present the world’s fastest 80C51 CPU at CeBIT. That event is a heart of the digital world, that’s why we wanted to present our CPU there, to gain reliable information from IT and ICT professionals," said Piotr Kandora, VCEO, Director of R&D in Digital Core Design.
The newest 8051 implementation, which is significantly much more efficient than any other solution available on the market. Independent tests were carried out on Dhrystone 2.1 benchmark program, which is the most representative of general processor (CPU) performance.
DCD’s DQ80251, the quad-pipelined ultra-high performance IP Core is 56.8 times faster than the original 8051 at the same clock frequency. – Our DQ80251 runs at 300MHz without losing's breath. It was possible not because of adding higher frequency, but thanks to unique architecture we implemented.
"I can just mention that original 8051, to get equivalent performance, must be clocked with 17000 MHz. Moreover, Polish Core provides up to 0.54311 DMIPS/MHz (VAX MIPS) and uses only 14 500 ASIC gates, which locates DQ80251 far away from other competitors. These unique features effect on DCD’s solution as a perfect choice for all embedded applications demanding cost effective and best possible solutions," said Thomas Krzyzak, vice president of Digital Core Design.
The DQ80251 family provides efficient real-time JTAG based DoCD debugger and is fully user configurable, which influences on its unique features, which are tailored to exact specification. Digital Core Design’s 8051 have been sold to hundreds of customers during the last decade, among them Intel, Siemens, Philips, Toyota or General Electric. They have been provided by DQ80251 family as a heritage of DP8051/DQ8051.
DCD’s DQ80251 family is available as VERILOG Source code, VHDL Source code and FPGA Netlist formats. As customers differ themselves, the same DCD’s IP Cores are designed in a wide variety of additional packaging and flexible licensing options.
Digital Core Design will present the 80C51 CPU from March 6 - 10, 2012 at CeBIT.