Market requirements are driving custom and analog/ mixed-signal (AMS) IC providers to develop ICs with ever-increasing complexity and performance. Current custom ICs are outgrowing the capabilities of conventional custom design techniques that involve traditional point tools, schematics, SPICE-level netlists, manual layout tools, manual routing, plus some scripting to improve design throughput. Design limitations are especially pronounced in the areas of hierarchical floor planning, signal and bus planning and routing, design change incorporation, and project coordination.
What about using advanced digital IC design tools to help automate the custom design effort? Advanced digital IC floor planning, signal planning, and routing tools rely on the highly standardized digital design ecosystem, and remain largely ineffective when faced with custom IC design challenges that include: irregular libraries, limited model availability, limited metal stacks, unusual physical topologies, extremely deep design hierarchies, lack of routing grids, lack of placement grids etc. Some of the approaches that have been used in digital design automation can be adapted to support custom IC signal planning and routing. However, don’t expect solutions from large digital IC design tool providers, the custom market space remains too small and too fragmented to justify the effort. Future solutions will largely come from smaller specialized custom design automation suppliers.
This article gives an overview of a proven methodology that relies on hierarchical custom design tools that can be used to resolve hierarchical signal planning and routing issues. The following topics will be covered: floor planning, power planning, bus long net and datapath planning, signal planning and routing, route fixing and optimization, and guided design flows.
The main starting point for optimizing hierarchical signal planning and routing involves hierarchical floor plan optimization. Floor planning for custom designs requires a great deal of flexibility, so support for both top down and bottom up approaches is needed to help optimize routing paths, soft macro (block) floor plans and soft macro (block) pin placements.
From a top down perspective, top-level pins that have fixed positions, such as I/O-related signal pins, should be visible to the rest of the design in order to help optimize associated routing and soft macro pin positions. From a bottom up perspective, designs often contain hard macros or intellectual properties (IPs) with fixed pin positions that should be placed in specific optimal locations. These bottom up, hard macro locations and pin positions should be used to help optimize soft macro pin positions and related signal routing. Floor planning is an iterative process, involving many possibilities and permutations, and using an automated tool that supports rapid hierarchical floor plan generation for custom designs will hasten the process. Early floor planning steps usually involve fixing hard macro positions based on I/O pins and dataflow, since these will impact more flexible parts of the design. The next steps involve sizing soft macros and performing trial and error block and pin placement to refine the floor plan.
After determining the basic floor plan and block sizes, the initial power plan should be added to the design. Aside from hard macros that contain internal power and ground routing, the power plan is normally added in a top down manner. The power and ground mesh should always be added before signal and bus routing, otherwise resources needed for power routing may be blocked by the signal routing. For custom designs with extremely limited metal layers, where the power routing is on the same layer as the signal routing, the power routing should be added before defining the block-level pin locations, otherwise power pin positions may be blocked by signal pins.
Power planning parameters can be easily defined using a GUI-based power planning tool that supports working at a high level of abstraction by creating power guides for all power domains. These power guides can include attributes such as (absolute/relative) location and shape, power supply names, routing layers, routing widths, via topologies, etc. Once defined, the power nets can then be pushed down into the soft macros for use by their design teams. When the design is reassembled, the soft macros are brought back into the top level and connected to corresponding top-level supply routes.
Bus and Long Net and Datapath Planning
The next major step involves adding top-level buses. This is best achieved using a bus planning tool (e.g., the Pulsic Unity Bus Planner) that allows users to quickly input top-level GUI-based bus guides, which provide information used to define and optimize the top-level routing paths of corresponding buses. Signal routing for each guided bus follows the same topology, and uses the same layer and vias. Those buses that don't require routing guides can be routed as ordinary signals.
Inputs for bus guidance include: physical topology, signal ordering, optional shielding, optional signal interleaving with other buses, metal layer selection, via selection, and via topology selection for forward or backward via sets, etc. Various generic controls can be provided by an attribute editor that can define buses by combining signals together; set signal routing widths and set signal route spacing; select X, Y routing layers; etc. Bus bits also can be reordered to help minimize cross-talk effects.
Once the bus guides are in place, the buses can be routed. Afterwards, the topology-based repeater planner (a bus planner tool feature) can specify locations for bus repeater insertions needed to speed up signal propagation and minimize cross-talk effects. The next step involves automatically placing and connecting the repeaters to the existing bus routing. By design, propagation delays for signals on the same bus will be very close since their routing and buffering remain similar.
Figure 1: Example of bus routing guides for two buses. Notice that the horizontal bus guides overlap. This indicates that the horizontal routes for the two buses are to be interleaved.
Figure 2: Bus signal routing for the two bus guides in Figure 1. Via ordering can be selected to minimize metal crossings when buses change routing directions.
Signal Planning and Routing
Signal planning is a time-consuming process that often impacts design schedules and area requirements for hierarchical custom designs. This process would benefit from the use of a comprehensive signal planning tool such as the Pulsic Unity™ Signal Planner that supports two modes: strictly-biased routing and multiple-bias routing that employs a jumper layer. Strictly-biased mode limits signal routing to user specified X and Y routing layers without exceptions, and is a capability provided by many routing tools. The multiple-bias routing mode is an advanced capability that supports signal routing on the same metal layer for both X and Y directions. At the same time, a jumper layer can be defined and used to cross other signals that are blocked by potential X or Y multi-biased routing. Processes with limited metal stacks that include a high resistance routing layer could use the high resistance layer as a jumper layer, thereby increasing available routing resources without seriously degrading timing.
Designers can employ biased routing capabilities to create various complex space-saving routing topologies, such as “L”, “C”, “J”, “H”, etc. Furthermore, signal routing can be stacked into elaborate patterns for processes with deeper metal stacks. Differing biased-signal planning attributes can be applied to different signals so that designers can customize routing in different parts of the design.
The following routing capabilities can be used to automate custom signal routing.
A shape-based router that supports Manhattan or angled routing and views the entire database at one time. It sorts and orders nets to minimize crossings and produce straight routes, unlike typical bin-based routers, which may detour signals through less congested routing bins.
A bus planner-router to support bus guidance, bus routing and repeater insertion.
A global router that provides rapid congestion analysis needed to optimize channel sizes.
A spine and stitch router for designs with long, thin aspect ratios and limited routing resources. A single spine route would be made in the resource-limited direction; perpendicular stitch routes plus vias are then used to connect the spine route to the loads.
Figure 3: An Example of a spine and stitch route. The horizontal spine route is in a resource-limited direction, while perpendicular stitch routes make the connections to the loads.
Route Fixing and Optimization
After the design is routed, some post-route optimization and error fixing is normally required. A smooth routing command removes unnecessary vias, jogs, corners, and segments while evening out the spacing between adjacent routes, which boosts production yields. The design database is automatically checked by an internal design rule checking (DRC) tool that ensures that the routing in the final routed database will pass DRC checks run at verification. Automated checking and fixing capabilities for antenna violations and layer density are also provided.
Guided Design Flows
Custom design projects have inherently diverse design tool requirements, forcing custom design automation tools to provide a wide variety of features and capabilities to meet the needs of widely differing custom design projects. Only a limited subset of these commands, options and settings would be applicable to any particular design project.
Guided design flows such as those in the Pulsic Unity Chip Planner are essential for making custom design automation software tools easier to use. Guided flows can provide the necessary step-by-step design automation commands needed to work on a targeted custom design while bypassing design tool features, capabilities, and/or flow steps that aren't needed. This simplifies custom design flows and reduces the learning curve.
SummaryTo meet the demands of increasing complexity and performance for custom and AMS ICs, custom designers will benefit from a proven methodology and hierarchical custom design tools with the following signal planning and routing capabilities:
A diverse set of hierarchical signal planning and routing features that support top down and bottom up approaches.
A hierarchical design database supporting seamless block and pin placement plus optimization.
Rapid hierarchical prototyping to explore “what-if” scenarios.
Automated routing solutions including: spine and stitch, shape-based, multi-topology, and multiple-biased routing.
Post-route optimizations: via and jog minimization; automated checking and fixing for DRCs, metal density, and antenna violations.
User-friendly guided design flows.
About the Author:
Bob Eisenstadt, Senior Technologist, Pulsic, Inc
Prior to joining Pulsic, Bob was Principal Engineer at Rambus and at Alchip. He has held senior design roles at Qthink, Silicon Image, 3dfx, SGI, VLSI Technology and was co-founder of Silicon Mosaic where he developed and patented an early low power design solution. Bob holds a BSEE from Cornell University plus an MSEE and an MBA from Santa Clara University.
Article Courtesy: EDA DesignLine