Digital Core Design, an Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house in Poland, has announced its latest UART core. The name may suggest that it is only for 950, but it also offers full compatibility with the most popular industry standards: 450, 550, 650, 750 and of course 950.
DCD’s IP supports IRDA data format mode, which combined with unique multitasking makes this IP Core one of the most advanced and flexible UART core.
The D16950 enables Fast Mode - when normally 16 samples per bit are being sampled, then in Fast just 4-15. The core is perfect for applications, where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, said says Jacek Hanke, CEO Digital Core Design.
It is also a proprietary solution for standalone implementation, where many UARTs are need to be implemented inside a single chip, and driven by some off-chip devices. Thanks to universal interface, D16950 core implementation and verification are very simple, just by elimination a number of clock trees in complete system.
The D16950 UART is functionally identical to the OX16C950, and allows serial transmission in two modes: UART mode and FIFO mode. In the second, internal FIFOs are activated, allowing 128 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes.
The D16950 includes also a programmable baud rate generator, which is capable to divide the timing reference clock input by divisors of 1 to (216-1) and produce a n × clock for driving the internal transmitter logic. Provisions are also included to use this n × clock to drive the receiver logic. DCD’s IP Core is also equipped with complete MODEM-control capability and processor-interrupt system.
It is fully customizable - interrupts can be programmed in accordance to specific requirements, minimizing the computing required to handle the communications link.
Like the other UART cores from DCD, the D16950 includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.
For more information visit http://dcd.pl/ipcore/130/d16950/ and for a datasheet see http://dcd.pl/workspace/documentation/ gen/d16950_ds.pdf