As Ethernet proliferates in the networking space, the adoption of Power-over-Ethernet (PoE) is rapidly spreading in both 10/100 and Gigabit Ethernet ports. The benefits and cost advantages of powering remote devices over Ethernet cable enables a wide range of applications, including IP telephony, digital video surveillance, wireless LAN access points and other low voltage network connected systems. A typical PoE system utilizes power-sourcing equipment (PSE) to send DC voltage over Ethernet twisted pair to a remote powered device (PD). As PoE systems are frequently exposed to transient voltage threats, protecting the Ethernet physical layer transceiver (PHY) from overvoltage stress is an important design consideration.

While PoE applications are increasing, the Ethernet PHY geometries are shrinking at a remarkable pace. Today, 90nm technology is common and silicon vendors are unveiling Ethernet PHYs on 65nm process technology with a view toward even smaller geometries. Implementing effective chip-level ESD protection on CMOS proves impractical at these advanced transistor geometries. The silicon area required for system level robustness is not only deficient, but implementing effective chip-level protection is uneconomical. Consequently, today's Ethernet-based system designs increasingly requires better off-chip circuit protection to meet worldwide compliance standards and to ensure system reliability.

Transient Voltage Threats
Ethernet interfaces are vulnerable to many different types of transient over-voltage events. Most common among these are ESD, cable discharge and lightning surges. In addition, the application of DC power over twisted pair cable on Power-over-Ethernet systems can introduce some unique differential-mode connection fault transients.

ESD is a very fast transient pulse. The rise time of the ESD waveform as modeled by IEC61000-4-2 is 700 picoseconds to 1 nanosecond while the pulse duration is 60 nanoseconds to 50 percent decay from the peak pulse current. The high current spike and the energy contained within the transient can easily render damage to the submicron input structures of silicon ICs.

Cable discharge (CDE), also known as cable ESD (CESD), occurs when an Ethernet cable becomes charged through routine interaction with the environment through the triboelectric effect or induction. The danger is present when the charged cable is plugged into the system interface. It has been shown that the discharge to the Ethernet port will present differential mode surge through the Ethernet magnetics¹. Similar to ESD, cable discharge exhibits a fast rise time (less than 1 nanosecond); however, unlike ESD, the ensuing waveform presents a long period of ringing with rapid polarity changes. Thus, the energy within a cable discharge waveform can pose more significant and problematic for an Ethernet designer than human body ESD.

On network connections, lightning surge is a routine threat. Lightning strikes can induce high voltage pulses onto Ethernet lines that can be transferred to the Ethernet PHY. Unlike nanosecond ESD events, lightning surge presents microseconds of pulse energy. The pulses are modeled by the EMC community as combination waveforms described with a rise time in microseconds, a peak pulse current and a fall time from the peak pulse current. The energy within an induced lightning strike is orders of magnitude greater than ESD level strikes.

Differential Mode Transients on Power-over-Ethernet Applications
As mentioned above, protecting Power-over-Ethernet interfaces can be especially challenging since, in addition to transients from ESD and surge, there are several scenarios that frequently occur where connecting DC power results in a differential surge on the Ethernet transmission line. This, of course, can cause catastrophic failure to the PHY or, a subtle problem, severe stress leading to latent IC failure. Most PoE circuit designers design some form of common-mode protection to protect the PoE circuitry. This usually involves the use of common-mode capacitors connected to earth ground, or possibly a TVS transient voltage suppressor across the power source with a very fast Schottky diode to direct the current flow to ground. Unfortunately, many designers make the mistake of overlooking differential mode protection. Ethernet differential pair utilize transformers and sometimes common mode chokes to isolate the PHY from the outside environment. The transformer provides a high level of common mode isolation to external voltages, but will provide no protection for metallic or differential (line-to-line) surges.

As shown in Figure 1, in a PoE system +48V or -48V will be present on the differential pairs. This DC voltage is common within a signal pair, resulting in a 0 DC voltage differentially. However, in some cases it is possible to introduce transients when power is connected. For instance, when the RJ-45 pin-connection is established between the power source equipment and the powered device, pin-to-pin mating may not occur simultaneously. At the instant the pins make contact to the RJ-45, it is possible to establish contact to pin 1 at an instance just prior or after contact is made to pin 2. This can result in a 48V differential transient with respect to the line pair, thus causing disruption or damage the PHY of the PoE circuit. A similar example may arise when a user switches connection from a powered device to a non-powered device on the same power source port. When the power source device detects that a non-powered device is now connected, there can exist some latency for the power source device to disable power to that port. In this case, power can be present for sufficient duration that a non simultaneous connection of the pins results in a 48V differential potential. This resulting differential-mode transient poses potential disruptive or destructive effects to the PHY.