As semiconductor manufacturers introduce new wireline transmission devices built on smaller CMOS geometries, more circuit protection challenges are emerging. This article explores five frequently asked questions regarding the basics of ESD and transient voltage suppression for board level circuit protection on dataline communication circuits.

1. "Do I really need a circuit protection device to protect my system from ESD?"
Years ago, a designer could probably get away without external protection devices, but today's systems are different. Systems have I/O interfaces, of course, and I/O interfaces are driven by advanced submicron semiconductor integrated circuits (ICs). So, the challenge is to protect ICs connected to system I/O interfaces from transient overstress. And, indeed, this is an increasingly complex challenge as communications ICs become faster and more efficient, but also highly sensitive to electrical overstress (EOS).

In the past, many engineers could rely on good layout technique and employing a range of "tricks" for EMC/ESD immunity (guard traces, ferrites, etc) to "harden" systems against ESD threats. This approach is rapidly becoming the exception, as the ICs employed into current- and next-generation systems are even more vulnerable to ESD than at any time in the past.

Currently, most tier 1 and tier 2 electronic equipment manufacturers recognize the tradeoffs, understand the value of time to market, and opt for using good low-clamping off-chip protection to safeguard their systems from electrical overstress. It's true that protecting system ports adds some cost to the BOM, but it can save test engineers from experiencing the agony and panic of debugging a system in the compliance phase, while the market window for the product is shrinking quickly. Given this tradeoff, it is natural to conclude that the cost of insurance is more economical in the long run.

2. "The transceiver in my design is rated for 2kV ESD. Isn't this sufficient?"

Probably not. In order to ensure safe handling through the semiconductor manufacturing process, IC manufacturers typically design ESD protection structures at the I/O cells of their transceivers. This "on-chip" protection prevents manufacturing operators who handle the die during assembly and test procedures from rendering damage to a statistically high number of IC devices.

Unfortunately, the 2kV built into the transceiver IC at chip I/O cells is not a good metric for evaluating system level transient immunity, nor should it be relied upon for system level immunity. Several different ESD immunity standards are used in the electronics industry, each one describing appropriate immunity levels for the intended ESD environment. For chip level (device level) ESD, the standard generally used is the JESD22-A114E standard. This JEDEC human body model (HBM) standard is what the transceiver manufacturer designed according in during the development of their chip. This standard is intended to ensure a minimum level of on-chip protection required for safely handling ICs on the manufacturing floor.

In contrast, at the system level an altogether different standard - IEC61000-4-2 - should be considered. IEC61000-4-2 describes and models the ESD threat level encountered at the system environment with fully packaged ICs operating in a complete electronic system. As can be expected, to model 'real world' system ESD threats, the IEC standard is a more severe ESD immunity test. IEC calls for four contact test voltages for different threat levels: ±2kV, ±4kV, ±6kV, and ±8kV with peak discharge currents as high as 30A. JEDEC and IEC standards call for different peak pulse current levels. While a 2kV ESD pulse according to JEDEC is probably sufficient ESD immunity threshold for a highly controlled manufacturing floor and ensuring that an acceptable level of ICs migrate through the process unharmed, it represents an insufficient level of protection for the system environment and should not be used as a design guide to protect against system level ESD strikes.

3. "If I want to design with ESD protection devices, what type of device should I look for?"

There are many devices on the market for transient voltage protection. There are many different technologies as well: polymer devices, multi-layered varistors (MLVs), transient voltage suppression diodes (TVS), gas discharge tubes (GDTs), zener diodes, and others. Each device technology presents advantages and tradeoffs. For mitigating electrical stress on low-voltage dataline communication circuits, for example, TVS diodes offer the most optimized balance between low clamping voltage and low capacitance. TVS diodes will respond to the transient faster than other protection technologies. As today's circuits are more delicate to EOS than previous chip design generations, a fast response time is critical.

It is important that we define clamping voltage. Clamping voltage is the voltage that will be seen by the IC after the protection circuit has engaged the transient and clamped the voltage. This can be thought of this as how well a protection device can "knock down" a transient voltage spike on a dataline. The TVS device operates as a shunt element on the dataline. When a transient spike presents on the line, the TVS diode junction breaks down in a sub-nanosecond response time to shunt the transient current away from the protected IC and clamp the transient voltage. Figure 1 presents a conceptual example of ESD voltage, in this case, clamped to a low voltage threshold. What is apparent from the diagram is that lower clamping voltage can be related to a higher level of protection.

A closely related parameter in transient voltage suppression elements is working voltage. The working voltage, sometimes called the reverse standoff voltage (Vrwm), is the nominal voltage below which the TVS device presents a high impedance state and appears nearly "transparent" to the dataline. When the voltage on a dataline exceeds the working voltage, as is the case during a transient, the protection begins to clamp the voltage spike. This is not to be confused with the clamping voltage, but it is the inflection point between a high-impedance state and a low impedance shunt element. All shunt protection devices are non-linear I-V curve devices as illustrated in Figure 2. A lower working voltage correlates to a protection device's ability to engage to the transient more quickly. This is essential in protection circuitry as there is a general correlation between lower working voltage and a resulting lower clamping voltage.