In addition to contributing to a lower clamping voltage, low working voltage circuit protection is also critical for another reason, mainly the consideration of the on-chip ESD protection structures. Consider the circuit shown in Figure 3. This diagram shows a dataline connected to a representative I/O pad at the input of a transceiver IC. It is important that the external protection TVS device engage the transient before the "on-chip" protection element triggers.

If the "on-chip" ESD structure at the chip I/O responds more quickly to the transient than the external protection component, the transceiver IC sees the initial brunt of the transient stress. And, of course, the whole idea of our protection device is to divert that energy, or as much as possible, away from the transceiver IC. Choosing devices with a lower working voltage is one way to safeguard from such a scenario. There are next generation TVS devices that are achieving remarkably low working voltages, even as low as 2.5V.

4. "What clamping voltage is needed to adequately protect my system?"

It's unfortunate, but transceiver IC datasheets (the devices that need to be protected) generally do not provide transient voltage immunity ratings. A new engineer, fresh on the job, might be tempted to look at the absolute maximum voltage rating provided on the datasheet as a reference for the maximum voltage that the IC can withstand, but this DC spec has no relationship to the voltage or current level that can be sustained for a transient pulse. Likewise, it is a mistake to try to correlate the 2kV HBM JEDEC rating of a transceiver IC to a system immunity level. There are simply too many variables at the system level.

So the question of "How much energy can my system interface survive?" is a very good one, but not an easy one to answer. There is no perfect way to make this determination other than to test the system to the worst case transients expected for its operating environment. One thing is certain: the lower the protection circuit can clamp the transient voltage, the better the protection and the more protection margin it will provide for the system.

Lowering the clamping voltage will minimize the energy that the IC must bear during the transient. With transceiver IC geometries shrinking, it's not uncommon for a few volts of reduced clamping voltage at the peak pulse current (Ipp) to protect an IC from latch-up, system upset, degradation, or worse, catastrophic transceiver damage. However, to understand the limits for a particular system interface, there's no substitute for testing the system.

5. "How should I think about placing the TVS component for optimal board layout?"

A good layout is very critical for transient protection performance. When the system is dealing with a fast rise time transient, such as ESD, taming the initial transient spike is highly dependent upon the quality of the PCB layout. Even a very good protection circuit may not overcome a poor layout. Here are some things to consider when going to layout with an external protection solution:

• Place TVS components near the interface connector, when possible. This will help suppress the energy at the entry point of the PCB and will reduce the possible secondary effects from radiated emissions from the ESD event
• Minimize parasitic inductance by running a shorter trace length from the TVS device to the protected I/O line. Considering that the rise time of a simulated ESD event is 1ns, a 30A pulse (IEC 61000-4-2) on a 1nH series inductance trace can raise the clamping voltage of the device by 30V.
• If possible, make ground connections from the TVS device directly to the ground plane. If vias are required, multiple vias to the ground plane are suitable.
• Given high-speed digital signals, the capacitance of the TVS device becomes an important consideration. To preserve signal integrity, select devices that will present minimal capacitive loading without sacrificing clamping performance.


• When available, use flow-through packages on high-speed interfaces. These packages allow for placing the protection component directly over the PCB differential pair. This eliminates stubs and unnecessary bends in the traces, which helps preserve signal quality. Figure 4 shows an example of how flow-through packages can be implemented.

The challenge of protecting today's systems from transient threats is more complex than ever before. However, careful selection of low-clamping voltage TVS components and paying attention to a clean layout, can ensure that a system is adequately safeguarded against electrical transient threats.

About the Author
Timothy Puls is a product-marketing engineer at Semtech Corporation and is responsible for transient voltage protection solutions for the communications infrastructure. Timothy holds a bachelor's degree in electrical engineering from Texas A&M University.