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TechOnline India > Skip Navigation LinksDesign & IP
Design & IP
EMA automates library creation process for engineers, PCB designers
This is an application automating the creation of both schematic symbols and the corresponding PCB footprints / land patterns, reducing library creation to a fraction of the time.
  • Accellera announces IEEE 1666 SystemC language standard for ESL available for free download
  • PowerSoC solves switch-mode DCDC noise and space issues
  • Magma, MunEDA pact for analog, digital designs
  • Blue Pearl announces release 6.0 of EDA software suite
  • Mathworks expands system design capabilities in MATLAB
  • Real Intent announces v1.5 of Ascent Lint software
  • Successful Adoption of DFM
  • Bridging software and hardware to accelerate SoC validation
  • Design networks for wireless M2M applications
  • Power Intent Formats: Light at the End of the Tunnel?
  • An introduction to wireless sensor network concepts
  • Fixing concurrency defects in multicore design
  • Xilinx launches first Targeted Design Platforms for accelerating systems development and integration
  • How to go about selecting a microcontroller
  • Circuit verification challenges in physical verification
  • LDRA tool suite integrates with Altera’s Nios II embedded design suite
  • Location Is Everything: Improving Performance with Interactive LDE Estimation
  • The Fast Track to 3D-IC Testing
  • How to design a traditional radio
  • EMA automates PCB footprint generation
  • Posedge unveils ‘Multifunction Non-Volatile Memory IP Platform’ for SoC designers
  • How formal MDV can eliminate IP integration uncertainty
  • Single event effects (SEEs) in FPGAs, ASICs, and processors
  • EnSilica announces design centre in Bangalore
  • How to design secure USB-based dongles
  • Reducing signoff corners to achieve faster 40-nm SOC design closure
  • 10 notable blunders of 2011
  • Critical area analysis and memory redundancy
  • Digital routing for 28 nanometer
  • FPGA Prototyping: HDL migration and FPGA Debug
  • Combining prototyping solutions to solve hardware/software integration challenges
  • Scan stitching of a complex hierarchical design: A case study
  • Challenges in static verification of low-power architecture
  • Change to 28-nm and 20-nm picking up pace: Mentor's Rhines
  • Gesture recognition--first step toward 3D UIs?
  • Embedding HPC: A rocket in your pocket
  • Evaluating PCB layout tools: A board developer’s perspective
  • Using the clock period constraint to your advantage
  • Synopsys to buy Magma for $507 million
  • Transfer from FPGAs for prototype to ASICs for production
  • Wipro wins Mentor PCB Technology leadership award
  • Add graphics without using a dedicated graphics controller
  • How to build a better DC/DC regulator using FPGAs
  • Addressing the new challenges of ASIC/SoC prototyping with FPGAs
  • Hardware/software design requirements planning: Part 1 - Laying the ground work
  • Efficient timing closure by reducing timing corners
  • Hunting noise sources in wireless embedded systems
  • A charging approach to increase runtime in portable applications
  • FPGAs for meeting size, reliability, security goals in medical devices
  • Integrated tools streamline low-energy MCU development
  • Assertion-based verification in mixed-signal design
  • Mistral launches its latest EVM, based on TI's DM814x/AM387x SoC
  • Doing C-code generation better: from graphical code to embedded target
  • Validating your GNU platform toolchain: tips and techniques
  • Soctronics claims 28-nm design win
  • Direct diagnosis for compressed ATPG patterns: A successful industrial experiment with layout-aware diagnosis
  • Meet the SERDES challenge: Design a high-speed serial backplane
  • Agile hardware development – nonsense or necessity?
  • Improving performance using SPI-DDR NOR flash memory
  • Startup offers embedded memory IP
  • Minimizing yield fallout by avoiding over and under at-speed testing
  • Reducing turnaround time with Hierarchical Timing Analysis
  • Programmable oscillators enhance FPGA applications
  • A practical approach to IP quality inspection
  • Open-Silicon takes broad ARM license
  • Arasan Chip Systems introduces USB 2.0 HSIC PHY IP
  • ESC Sneak Peek: Discover tools you can use
  • Cosmic announces 28-nm roadmap
  • Open-Silicon gets patent for low power ASIC design methodology
  • Altera demos floating-point DSP flow with FPGAs
  • Imec India identifies three projects to work on
  • Designing with core-based high-density FPGAs
  • The key to realizing full multicore design functionality
  • Transitioning to multicore processing
  • Making embedded processing development easy - part 4
  • Cosmic Circuits tapes out MIPI MPHY in 85nm
  • Mentor Graphics to expand India operations
  • Students win Synopsys design competition
  • e-MMC vs. NAND with built-in ECC
  • Standardization in software tools boosts development of next generation applications
  • Resolving partitioning challenges
  • Initiative to help EEs find the right Apps
  • Silego’s GreenPAK – Design and program a custom chip in minutes
  • There’s a stack for that: FNET provides TCP/IP protocol
  • Automatically generate C code
  • Making embedded processing development easy
  • Synthesis challenges with scan compression logic
  • Latches and timing closure: a mixed bag
  • Ultra-low power microcontrollers for compact wireless devices
  • X-FAB design IP Blocks speed dev times for MEMS accelerometers
  • MIT Professor uses ESL tools and FPGAs to teach system architecture
  • Cosmic partners with Newlinktek for IP sales
  • Understanding clock net routing with shrinking technology
  • Hardware-based virtualization eases design with multicore processors
  • Understanding embedded system-boot techniques
  • Building mobile and embedded consumer devices that can "see"
  • Managing power in embedded applications using dual operating systems
  • Reduce SoC device/package leakage/power with improved power management protocols
  • Debug a microcontroller-to-FPGA interface from the FPGA side
  • Things change, things stay the same: Finding unity in a multi-faceted world
  • It's the software...unless it's the hardware
  • ARM buys Texas processor verification firm
  • A novel architecture for Home Area Network devices
  • Emulation unbound
  • Software and hardware challenges due to the dynamic raw NAND market
  • Bring big system features to small RTOS devices with downloadable app modules
  • Basics of I/O design in the age of SoCs: Part 1 - The building blocks; Part II - Hot swap and other implementation issues
  • The 'internet of things' is driving demand for mixed signal MCUs
  • Android aat ESC 2011: Deja vu all over again?
  • The best of both worlds
  • Two methodologies for ASIC conversion
  • Measuring return on investment of model-based design
  • Making hardware more like software
  • ASIC prototypes on time—or your money back
  • MIPS, Carbon team on cycle-accurate CPU virtual platform
  • VMM based multi-layer framework for system level verification
  • Achieve your SoC Design Goals – Measure Twice, Cut Once!
  • Time to exploit IDEs for hardware design and verification
  • Embedded software unites old and new
  • Securing nonvolatile, nonresettable counters in embedded designs
  • Functional safety poses challenges for semiconductor design
  • Eurotech's CPU-1440 low power PC/104+ board includes ISA and DOS Support
  • Cadence opens PCB EDA to Apple biz model
  • Differentiating your Android-based embedded device
  • Choosing the right OS for your medical design
  • Validate hardware/software for nextgen mobile/consumer apps using software-on-chip system development tools
  • Mistral joins TI's Elite Design House Network
  • Why your embedded controller may not need a CPU
  • Android, Linux & Real-time Development for Embedded Systems
  • Adopting C programming conventions
  • Challenges of safety-critical multi-core systems
  • DSPs with PCI Express interface extend connectivity while improving performance and power efficiency
  • Don’t let analog/digital misinterpretations put your design in jeopardy
  • 8-bit MCUs provide cost effective, efficient high-brightness LED control
  • Architecting the smart grid for security
  • Testing times for LTE – can it co-exist with 2 and 3G systems?
  • Cadence IP targets DDR4 in SoCs
  • Using verification coverage with formal analysis
  • Small-signal bandwidth in a big-bandwidth era
  • Trip over threads to trap multicore bugs
  • Using trace to solve the multicore system debug problem
  • How to achieve quality assurance for your electronic designs
  • Non-intrusive debug and performance optimization for multicore systems
  • Is lock-free programming practical for multicore?
  • Scalable TLM Delivers the Benefits of ESL
  • Attofarad accuracy for high-performance memory design
  • Correlating to good effect
  • Making the transition from C to C++
  • What makes an optimal SoC verification strategy
  • Using simulation and emulation together to create complex SoCs
  • Overcoming the challenges of multicore software development
  • Using PCI Express as a fabric for interconnect clustering
  • Hardware/Software integration: Closing the gap
  • Google demos tablet version of Android
  • How PTS benefits embedded systems designs
  • Lower the overhead in RTOS scheduling
  • Open-Silicon enhances Interlaken IP core for very high-speed chip-to-chip serial interfaces
  • Model-driven development for multicore-based software
  • Beyond cores: Unlocking multicore’s full potential
  • Expediting processor verification through testbench infrastructure reuse
  • An elegant testbench driver modeling for the verification of a configurable IP
  • Mixed abstraction furthers HLS advantage
  • Implementing high speed Serial interfaces in FPGA using HAPS Platform
  • Cosmic announces portfolio of 14-bit ADC IP cores for measurement, communication apps
  • It takes two to tango: Simplifying Linux/WinCE real-time applications development using 8- and 32-bit low-cost microcontrollers
  • USB simplified - adding USB connectivity to applications with legacy serial connections
  • ARM plays catch-up in graphics IP
  • Next-generation hot-swap controllers - a programmable approach
  • Achieving first day multicore SoC software success
  • 7 myths of analog and mixed-signal ASIC design
  • e-con Systems announces Android support for camera daughter boards
  • An RTL to GDSII approach for low power design: A design for power methodology
  • Optimiizing embedded applications using DMA
  • FPGAs pave the way for consumer-targeted PICO projectors
  • Hyper pipelining of multicores and SoC interconnects
  • Making a product people want - inspired concepts in capacitive touchscreens
  • What next for microcontrollers?
  • Design implications of Energy Efficient Ethernet (EEE)
  • A next-gen FPGA-based SoC verification platform
  • Restoring the artistry of analog design
  • Carbon IP Exchange streamlines access to virtual platform building blocks
  • New variants of dSPACE MicroAutoBox II tout powerful I/O, FPGA board
  • Cadence sketches out tools vision
  • AMI models: What, why and how?
  • DSP options to accelerate your DSP+FPGA design
  • How ro reduce board management costs, failures and design time
  • WinPE 2.1 - much more than a tool
  • Processor reorder buffer timeout - a debug guide
  • MIPS Technologies touts MIPS32 1074K core as fastest fully-synthesizable multicore IP
  • Latest Xilinx ISE Design Suite supports plug-and-play ASIC-FPGA design
  • Using the application modeling and mapping methodology for system-level performance analysis
  • Functional coverage methodology
  • Tech group opposes offshoring bill
  • Unpack, switch on and get going
  • Hunting that elusive bug
  • How to achieve timing closure in large, complex FPGA designs
  • What is digital power and what are its benefits?
  • How to achieve 1 trillion floating-point operations per-second in an FPGA
  • Conquering the memory bottleneck
  • Using switched capacitors to create programmable analog logic blocks in mixed-signal designs
  • Reusability, usability and flexibility
  • Harness speed, performance, signal integrity, and low current advantages of 65nm QDR family SRAMs
  • System Verilog configurable coverage model in an OVM setup – concept of reusability
  • MCU to Intel architecture conversion
  • The evolution of Java technology for Internet appliances and embedded devices
  • Partitioning an ASIC Design into Multiple FPGAs
  • Using in-design physical verification to reduce tapeout schedules
  • Treat programmable hardware design as a high level system task
  • High-level synthesis, verification and language
  • Medical Imaging Implementation Using FPGAs
  • System Level Software Centric Power Debugging using Virtual Prototypes
  • Product How-To: Making USB Flash drives secure: Why and How?
  • A monitor-based approach to verification
  • Code Coverage Convergence in Configurable IP
  • Product How-To: Incorporating quality into reusable IP
  • Guidelines for complex SoC verification
  • eInfochips ranked top chip design services provider by Gartner
  • Efficient interfacing with external memory in high-end video
  • Synopsys mulls spinoff for design kit initiative
  • Mentor wins DFM gig at GlobalFoundries
  • TSMC, SVTC collaborate on fast-track chip design
  • Will Tessera's 'smart module' gamble pay off?
  • Analyst: IC design outsourcing decline set to continue
  • OVP offers free simulation models of ARM processor cores
  • IMEC launches integrated solutions for technology exploration
  • EASIC offers ASIC-in-a-Box design kits
  • Design Hint: Reduce the clock-tree power drag in your circuit implementation
  • Virage rolls new interface IP products
  • Implementing cost-effective gigabit serial links over cable
  • Best of FPGA "lite" user guides
  • MCU Table
  • Seamless integration of multicore embedded systems
  • 97 Things Every Programmer Should Know
  • Mentor Graphics offers IP platform for FPGA designs
  • Failure not an option: Heading off chip flaws during design
  • Silicon circuit board seeks to replace ASICs
  • Virtual testing with model-based design
  • China cranks up fabless startup efforts
  • Processor architectures: Where will we will be in 2020?
  • Efficiently implement a Punctured Rate 1:4 Viterbi decoder on a Blackfin DSP
  • TSMC rolls analog design kit, EDA formats
  • Front end IC simplifies board design, reduces cost
  • Licensable IP houses leapfrogging DSP incumbents
  • Debugging of embedded Linux applications on ARM9/ARM11 processors
  • Startup to demo synthesis of asynchronous logic at DAC
  • Startup claims breakthrough in reconfigurable logic
  • Miminizing Power Consumption in RTL Designs Using Sequential Clock Gating and Low-Power Synthesis
  • Analysis: Oracle looks back to the future
  • Protecting software IP: what engineers need to know
  • Design quality enhances company survival
  • The ITRS process roadmap and nextgen embedded multicore SoC design
  • So You Have a Network Connection. Now What?
  • IP video surveillance standards
  • PRODUCT HOW-TO: Differential line driver with excellent load drive
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