TechOnline India Header
Most Popular
Top 5 Courses
  • Fundamentals of PCB Design
  • Paralleling DC-DC Converters
  • Fundamentals of x86 Architecture
  • Analog Devices' SHARC 32-Bit DSP
  • Analog eLab - Improved INA Input Filter
    Most Popular
    Top 5 Technical Papers
  • ARM Platform Technical Overview
  • Using C++ Efficiently in Embedded Applications
  • Top 10 Drivers for Embedded Android
    Most Popular
    Top 5 Webinars
  • Designing embedded HMIs and connecting them to hardware
  • 2009 Embedded Market Study
    All Articles Products Courses Papers VirtuaLabs Webinars
    Top Search Items
    C


    Techpaper Spotlight

    Wind River
    Accelerating the Development of Embedded Linux Devices with JTAG On-Chip Debugging
    /
        Login | Register | Welcome, Guest

    Topics
    POLL
    How much code have you produced in your career?
    A few KLOC
        38%
    100s of KLOC
        44%
    Millions of LOC
        11%
    A trillion
        7%
     
    Design & IP
    Reusability, usability and flexibility
    Discussions on reusability and reusable components are widespread among the practitioners of software engineering as well as the academia. A library of reusable components, one among the strategic engineering assets of any successful IT organisation contributes not only to productivity improvements but also to product quality throughout the life cycle of any software product.
  • Harness speed, performance, signal integrity, and low current advantages of 65nm QDR family SRAMs
  • System Verilog configurable coverage model in an OVM setup – concept of reusability
  • MCU to Intel architecture conversion
  • The evolution of Java technology for Internet appliances and embedded devices
  • Partitioning an ASIC Design into Multiple FPGAs
  • Using in-design physical verification to reduce tapeout schedules
  • Treat programmable hardware design as a high level system task
  • High-level synthesis, verification and language
  • Medical Imaging Implementation Using FPGAs
  • System Level Software Centric Power Debugging using Virtual Prototypes
  • Product How-To: Making USB Flash drives secure: Why and How?
  • A monitor-based approach to verification
  • Code Coverage Convergence in Configurable IP
  • Product How-To: Incorporating quality into reusable IP
  • Guidelines for complex SoC verification
  • eInfochips ranked top chip design services provider by Gartner
  • Efficient interfacing with external memory in high-end video
  • Synopsys mulls spinoff for design kit initiative
  • Mentor wins DFM gig at GlobalFoundries
  • TSMC, SVTC collaborate on fast-track chip design
  • Will Tessera's 'smart module' gamble pay off?
  • Analyst: IC design outsourcing decline set to continue
  • OVP offers free simulation models of ARM processor cores
  • IMEC launches integrated solutions for technology exploration
  • EASIC offers ASIC-in-a-Box design kits
  • Design Hint: Reduce the clock-tree power drag in your circuit implementation
  • Virage rolls new interface IP products
  • Implementing cost-effective gigabit serial links over cable
  • Best of FPGA "lite" user guides
  • MCU Table
  • Seamless integration of multicore embedded systems
  • 97 Things Every Programmer Should Know
  • Mentor Graphics offers IP platform for FPGA designs
  • Failure not an option: Heading off chip flaws during design
  • Silicon circuit board seeks to replace ASICs
  • Virtual testing with model-based design
  • China cranks up fabless startup efforts
  • Processor architectures: Where will we will be in 2020?
  • Efficiently implement a Punctured Rate 1:4 Viterbi decoder on a Blackfin DSP
  • TSMC rolls analog design kit, EDA formats
  • Front end IC simplifies board design, reduces cost
  • Licensable IP houses leapfrogging DSP incumbents
  • Debugging of embedded Linux applications on ARM9/ARM11 processors
  • Startup to demo synthesis of asynchronous logic at DAC
  • Startup claims breakthrough in reconfigurable logic
  • Miminizing Power Consumption in RTL Designs Using Sequential Clock Gating and Low-Power Synthesis
  • Analysis: Oracle looks back to the future
  • Protecting software IP: what engineers need to know
  • Design quality enhances company survival
  •  
    Latest Webinars
    · The Next Generation of Ethernet: How the New IEEE Standards Enable Energy Efficiency and Quality-of-Service
    · Simplified Physical Layer Receiver Test of Re-timed Architectures Such as USB 3.0, SATA, SAS, PCIe 2
    · How to solve the most common high-speed bus issues in embedded design on a budget
    · Early access to ARM Core Technology with Fast Models from ARM
    · Latest MIPI Standards: PHY and Protocol Testing Guidance
     
    Member Company Spotlight
    Luminary Micro
     

    Get hands-on experience with the latest VirtuaLab from Luminary Micro. Learn the features of the new Luminary Micro LM3S811 microcontroller and develop software with your choice of ARM/Keil RealView Microcontroller Development Kit, CodeSourcery G++ GNU development environment, or IAR Embedded Workbench for ARM. View the Luminary Micro LM3S315 / LM3S316 / LM3S611 / LM3S613 / LM3S811 Development System here.


    Member Companies