Commack, NY -- With an emphasis on high performance, small size and low power, Tensilica Inc. has introduced the ConnX D2 16-bit dual-MAC (multiply accumulate) DSP engine for its proven Xtensa LX dataplane processor cores for SoC designs.

The launch of the ConnX D2 comes just two months after the launch of the company's ConnX DSP line for 3G and 4G applications and represents a major push by Tensilica into broader communications processing applications, as well as low-power consumer devices.

A key feature of the new core is its compiler, in that any C code, including those written with C intrinsic functions for the TI C6x family or ITU reference code, can run unmodified and with "excellent performance" (see press release).

Any new processing engine has the potential to be sidelined quickly because of a lack of compatible code, shallow ecosystem and poor industry support, compared to more established architectures. That's not the case with the ConnX D2. According to Steve Roddy, vice president of marketing and business development, the company didn't go about reinventing the wheel, but instead focused on enhancing it, while enabling the use of a large base of existing C code.

"We don't have an existing legacy DSP architecture, so we can't say you can use all your existing code: but we did look at intrinsics for C code," he said. Specifically, those for the Texas Instruments C6x and ITU. "This gives us a large amount of industry software."

For full details on the implications of this capability and how to take advantage of those intrinsics on the ConnX D2, see the related technical paper.

With the large ITU software code base available, the ConnX D2 DSP engine is ideal for telecom infrastructure and VoIP, two of its target applications, along with home gateways, PBX switches and voice switches.) applications. With its small size (less than 70,000 gates), the customizable ConnX D2 DSP engine is also ideal for a wide variety of low-power portable consumer applications including mobile wireless devices, next-generation disk drives and data storage, home entertainment devices, and computer peripherals.

The core itself adds dual 16-bit MAC units and an 8-entry, 40-bit register file to the base architecture of the Xtensa LX DPU (dataplane processing unit) and supports a wide range of data types (e.g., 16-, 32-, and 40-bit integer and fixed point; 16-bit complex; 8- and 16-bit vector), seven addressing schemes, and data manipulation instructions including shifting, swapping and logical operation.

The ConnX D2 core uses a two-way VLIW SIMD architecture with a five-stage pipeline and can perform three logical functions per cycle. For a full market positioning and architectural overview, click here. Click on image to enlarge.

It uses two-way SIMD (single instruction, multiple data) instructions to take full advantage of vectorizable C code and implements an improved form of VLIW (very long instruction word) instructions and a five-stage pipeline.

"It can do two full MAC operations per cycle with code stored in parallel," said Roddy, which he pointed out translates to three logical functions per cycle.

Other key features include algorithm acceleration instructions, the ability to further customize the core using the Tensilica Instruction Extension methodology and complete tool support.

Performance and power consumption
When optimized for high frequency operation, an Xtensa processor with the ConnX D2 DSP engine delivers clock speeds up to 600 MHz in a 65-nm general-purpose (GP) process. When optimized for low-area in cost sensitive applications, a fully configured Xtensa LX with ConnX D2 engine can occupy as little as 0.18mm² (fully routed) in 65-nm GP process technologies. While core power consumption will vary with process technology and synthesis optimization targets, one example data point is that a fully configured Xtensa LX core with the ConnX D2 DSP engine consumes 52 μW/MHz in 65-nm GP process technology (measured running an AMR-NB (VAD2) algorithm).

When will it be available? October.