Building reliable, high-speed memory interfaces target FPGA I/O structures as well as intellectual property (IP) used within design software to allow rapid configuration of memory interfaces. These techniques use IP to help gain an extra timing margin at high speed operation.

External double data rate (DDR) memory types are a common part of many FPGA designs. This article will examine the architecture behind the I/O blocks in high-end FPGAs (i.e. Altera's Stratix IV devices) and how these FPGAs are able to achieve 533 MHz or 1067 Mbps data rates. It also examines the tools that are used to build a memory interface, and provide a brief overview of the timing budget.

These FPGAs support the five leading double data rate memory types, that is DDR1, DDR2, and DDR3 as well as QDRII+ and RLDRAM as well as other memory interface types. RLDRAM is supported at rates of up to 1,600 megabits per second or 400 megahertz, QDRII+ at 1,400 megabits per second, and DDR3 at speeds of up to 533 megahertz or 1,067 megabits per second.

Figure 1 illustrates the I/O block found in a high-end FPGA. It is comprised of six key areas (A, B, C, D, E, and F), each essential for reliably interfacing to high-speed external memories:

Position "A" " Dynamic on-chip termination (OCT)

Position "B" " I/O buffering

Position "C" " Variable I/O delays

Position "D" " 2:1/1:2 muxing/demuxing

Position "E" " Read/Write leveling blocks

Position "F" " Half-rate registers

Figure 1. Calibrated Dynamic OCT for Proper Line Termination and Power Savings (click on image to enlarge).

In the dynamic termination of the block (Position A expanded view, Figure 1 right side); the termination is used to swap between the parallel termination when reading or swapped to series termination when writing. In this way, the FPGA is always able to provide the ideal line termination for a switching bidirectional bus depending on its operation.

Being able to dynamically turn on and off the parallel termination not only provides for the proper line termination, but it also provides significant power savings. Power is saved compared to fixed external resistor configuration, which has a constant draw. By switching the termination when the bidirectional DDR bus is set to read the path to ground through the termination in the FPGA is effectively taken out of circuit, consequently saving power.