The earliest adopters of the Cortex-A9, ARM's semiconductor partners, have been implementing the processor core in low power processes, Schorn said. "Many partners are on LP processes so we were not going to duplicate what our partners have done. LP was about wireless. This high performance core provides the other axis with four or five times the Atom power efficiency," said Schorn.

The hard macro does not include a graphics processor but intriguingly the test chip being taped out does. "There is s a MALI-400 multimedia processor and a MALI-VE video engine on the dual-Osprey test chip," said Schorn.

Similarly the Osprey core does not include the Fast14 technology from Intrinsity Inc. (Austin, Texas) used to pump the Samsung implementation of the Cortex-A8 processor above 1-GHz clock frequency. "The Intrinsity technology is pretty fantastic. It has been applied to Cortex-A8 but it's not something we are offering here. It's certainly not ruled out in the future."

Osprey does include the clock gating and low-power design techniques used in in other ARM low-power processor designs. Major processing units consume no power if there is no instruction in the pipeline and the design comprises six independent power domains to manage leakage power when performance is not required. The integer pipeline can be can be turned off with SRAM retention to allow immediate reload possible and the cache snoop unit and L2 cache controller unit are also independently controlled.

Overall Schorn concluded: "This is big departure from what we've done in the past. It complements are partners and can expand application of the ARM architecture."

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