Multi-FPGA Implementation
The verification of larger ASIC designs requires the use of multiple FPGAs. There are a number of considerations that have to be taken into account when it comes to taking the RTL intended for an ASIC implementation and partitioning it across multiple FPGAs. For example, ASIC-centric constructs such as gated clocks have to be translated into their FPGA equivalents; ASIC memories have to be converted into FPGA and/or on-board memories; and so forth.

Another consideration is that it may be necessary to replicate portions of logic in order to overcome Input/Output (I/O) limitations or to achieve performance goals. Implementing these tasks by hand is resource-intensive, time-consuming, and prone to error. Furthermore, it results in two separate code streams that can lose synchronization, thereby resulting in functional differences between the FPGA-based prototype and the ASIC it is intended to represent.

In order to address these issues, it is necessary to be able to take an existing ASIC design and auto-interactively partition it across multiple FPGAs (Figure 1). Such a tool must be capable of working with Verilog, SystemVerilog, VHDL, and mixed-language designs. Also, the tool must automatically convert any ASIC-specific constructs (including any DesignWare instantiations) into equivalent FPGA structures.

Figure 1. A tool is required to auto-interactively partition the design.