Advanced FPGA Synthesis
Traditional synthesis technology is failing to address the needs of today's extremely large and complex FPGA designs implemented in devices at the 65 nm technology node and below. The problem is that conventional FPGA synthesis engines are based on ASIC-derived techniques such as floorplanning and in-place optimization (IPO) using proximity-based timing models.

These techniques are largely obsolete even in the ASIC world, and ASIC-derived physically-aware synthesis algorithms are simply not appropriate for use with the regular architectures and pre-defined routing resources presented by FPGAs. The end result is that traditional FPGA synthesis approaches require multiple time-consuming iterations between front-end synthesis and downstream place-and-route tools so as to achieve convergence and timing closure.

The solution to creating a physical synthesis solution that can truly handle the complexities associated with FPGA architectures is to approach the problem from a radically different viewpoint. The way this works is to characterize all of the tracks in the FPGA " including entry points, end points, and internal exit points " and to then build a "map" of all of these tracks. In the software world this type of map is referred to as a Graph; hence the reason why this technique may be referred to as graph-based physical synthesis (Figure 3).

Figure 3. Graph-based physical synthesis is required to handle the complexities associated with today's extremely complex FPGA architectures.

In addition to the tracks themselves, this map also includes details as to which LUT pins have access to which types of track, any differences in input-to-output delays through each LUT, and the size and locations of any hard macros in the device. Instead of looking for proximity, the graph-based physical synthesis engine focuses on speed using an interconnect-centric approach. Starting with the most critical paths and working its way down to the least critical paths (thereby ensuring that the fastest routes are available for the most critical paths), the graph-based physical synthesis engine will select tracks and their associated entry points and exit points; from these tracks it will derive placements; from the tracks and placements it will derive accurate delays; and it will then optimize and iterate as required.

The end result is a single-pass, push-button synthesis step requiring zero (or very few) iterations with the downstream place-and-route engines. Furthermore, based on the analysis of more than 200 real-world designs, is has been shown that graph-based physical synthesis can provide 5 to 20% performance improvement in terms of the overall clock speed of the system.