The Exception Vector Table
The exception vector table is where the application code tells the processor core the location of software routines to handle various asynchronous events. For ARM cores, these events include Reset (triggered by a power-up or hard reset), faults and aborts due to bus errors or undefined instructions, and interrupts triggered by either software requests or external sources such as on-chip peripherals.

For an ARM7TDMI, the exception vector table typically consists of at least six¹ branch² instructions in hand-coded assembly:

b	Reset_Handler
b	UndefInstr_Handler
b	SWI_Handler
b	PrefetchAbort_Handler
b	DataAbort_Handler
b	. ; Reserved vector
b	IRQ_Handler
b	FIQ_Handler

The exception vector table on the Cortex-M3 can be defined in C as an array of pointers (see Listing 1). The first entry is the address of the stack and the remaining entries are pointers to various exception handler functions.

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Processor modes
The ARM7TDMI has seven processor modes, six of which have their own stack pointer. One of the seven modes, User, operates at a lower privilege level than the others. The Cortex-M3, on the other hand, has only two modes: Thread and Handler. Thread mode can operate at either an elevated privilege level or a user level and can use either the main stack or the process stack. Handler mode always operates at privilege level with the main stack.

Elevated privilege levels allow access to the processor status registers (CPSR and SPSR on the ARM7TDMI; APSR on the Cortex-M3) and possibly restricted memory regions as dictated by an optional memory protection unit (MPU). Table 3 shows equivalent levels between the ARM7TDMI and the Cortex-M3.

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