Disabling interrupts
Occasionally, an application may need to temporarily disable all processor interrupts. On the ARM7TDMI, the vendor-supplied interrupt controller may provide a global disable register or the application may set the current processor status register "I" bit (and perhaps the "F" bit) with the assembly code in Listing 6.

View the full-size image

On the Cortex-M3, a special PRIMASK register disables all interrupts except the NMI and fault exceptions:

	disable_irq:	
mov
r0, #1	
msr
PRIMASK, r0	enable_irq:	
mov
r0, #0	
msr
PRIMASK, r0

But there is still more to do, if you want to get this job done by last Wednesday. To read about porting issue related to software interrupts, fault handling, the SWP command, instruction time, assembly language and optimizations, go on line and read Part 2: "An ARM programmer's work is not yet done."

Endnotes:
1. The FIQ handler can simply begin at offset 0x1c instead of a branch.

2. PC-relative LDR instructions can be used instead of branches for long jumps.

After receiving a BSEE from the University of Texas in 1992, Todd Hixon has spent most of his career developing hardware and software for various microcontroller-based products, eventually specializing in network device drivers for a major DSL modem manufacturer. He now works for Atmel where he provides specialized software solutions for Atmel's AT91 family of ARM microcontrollers.