Convergence of technologies

The challenges for developing a more power-efficient data recovery design lies within the principal circuit components, namely the field programmable gate array (FPGA) for circuit management, data control, and the flash memory for data storage and retrieval upon power recovery. Each of these components must support a power budget specified by the data recovery and restore circuit of the RAID adapter card.

Determining the FPGA and flash memory specifications is a function of the DRAM density that is backed up during a power outage (e.g. 2-8 GB) and the time available to store this data into flash memory, where the time constraint is driven by the available energy from either a battery or alternate green energy source like ultra capacitors.

With lithium ion battery backed designs, data can be stored over a period of 48-72 hours. This approach requires field resource maintenance to address the power outage within this timeframe without losing the data that was stored in flash memory by the battery backed RAID adapter backup circuit. Furthermore, battery disposal must be factored into the cost of supporting this type of design.

Power efficiency and performance advancements in FPGA and flash memory technology now make it possible to develop effective data recovery circuits in RAID adapter cards that can be charged from alternative charging sources like ultra capacitors.

FPGA Technology

The process technology used in Altera FPGAs has moved downward from the 65nm node to the 40nm node. Sharing the cusp of the technology curve with standard cell ASICs and full custom designs in microprocessor and associated chipsets, FPGAs are now being used in volume production computer and storage applications like high performance computing (HPC), I/O virtualization, high speed serial interface bridging, and memory backup/restore functions.

In addition, the latest advancements in FPGA architecture design and supporting power simulation tools have allowed increasing FPGA logic densities to be offered without the penalty of increased power consumption.

FPGA Architecture of the Cyclone III and its' low power attributes Click on image to enlarge.