TechOnline India Header
Most Popular
Top 5 Courses
  • Fundamentals of PCB Design
  • Paralleling DC-DC Converters
  • Analog eLab - Improved INA Input Filter
  • Fundamentals of x86 Architecture
  • Analog Devices' SHARC 32-Bit DSP
    Most Popular
    Top 5 Technical Papers
  • ARM Platform Technical Overview
  • Using C++ Efficiently in Embedded Applications
  • Top 10 Drivers for Embedded Android
    Most Popular
    Top 5 Webinars
  • 2009 Embedded Market Study
  • Designing embedded HMIs and connecting them to hardware
    All Articles Products Courses Papers VirtuaLabs Webinars
    Top Search Items
    C


    Techpaper Spotlight

    Wind River
    Accelerating the Development of Embedded Linux Devices with JTAG On-Chip Debugging
    /
        Login | Register | Welcome, Guest

    Topics
    POLL
    How much code have you produced in your career?
    A few KLOC
        38%
    100s of KLOC
        44%
    Millions of LOC
        11%
    A trillion
        7%
     



    Study gives mixed marks to high-level synthesis
    EE Times
    SAN FRANCISCO—High-level synthesis (HLS) tools for FPGA design deliver excellent results and are easy to use, but do not fully abstract users from the FPGA RTL tool flow, according to a study conducted by benchmarking and analysis firm BDTI Inc.

    In the study, created with help from FPGA vendor Xilinx Inc., BDTI engineers using HLS tools with an FPGA achieved results equal to an FPGA designed with RTL and 30 times better than a DSP processor, according to the firm said.

    But weaknesses in RTL tools prevent HLS tools from fully delivering on their promise, because HLS tools only accelerate a portion of the design flow, BDTI said. After generating RTL code using HLS tools, users still need an experienced FPGA designer to implement the code at the back end using FPGA design tools, the study found.

    Preliminary results for the BDTI Optical Flow Workload, as judged by maximum frame rate achievable at 720p resolution (source: BDTI).

    "High-level synthesis tools did a great job getting us from C to RTL, but once we are at the RTL point we had to take that RTL in a manual way through the traditional FPGA tool flow," said Jeff Bier, founder and president of BDTI. "Getting from RTL to a bit stream on the FPGA required a lot of expertise."

    HLS tools have been around for roughly 20 years, mainly for ASIC design, but have not enjoyed large-scale success, BDTI noted. This has resulted in widespread skepticism that they will ever deliver, according to BDTI.

    Bier said BDTI launched a program to evaluate HLS tools targeting FPGAs because processor users seeking high performance are being forced to move to multi-core chips, but parallel programming tools and techniques are immature. Also, many FPGA users are facing design-cost and time-to-market crises as designs get more complex because RTL design is difficult and time-consuming, Bier said. Making FPGAs much easier to use through HLS tools "could be a real game changer," Bier said.

    So far, BDTI has evaluated only two HLS tools: AutoPilot from AutoESL Design Technologies Inc. (Cupertino, Calif.) and Pico from Synfora Inc. (Mountain View, Calif.).

    1 | 2 | 3 NEXT >
     
     
    Latest Webinars
    · The Next Generation of Ethernet: How the New IEEE Standards Enable Energy Efficiency and Quality-of-Service
    · Simplified Physical Layer Receiver Test of Re-timed Architectures Such as USB 3.0, SATA, SAS, PCIe 2
    · How to solve the most common high-speed bus issues in embedded design on a budget
    · Early access to ARM Core Technology with Fast Models from ARM
    · Latest MIPI Standards: PHY and Protocol Testing Guidance
     
    Member Company Spotlight
    Actel
     

    Actel is attacking power consumption—from chips to systems—with its innovative FPGAs and PSCs, power-optimized tools, power-smart IP, and the industry's smallest packaging.


    Member Companies