Figure 9 is a conceptual layout diagram of National's LMH0384 3 Gbps/HD/SD SDI adaptive cable equalizer, LMH0341 SDI de-serializer, LMH0340 SDI serializer and a FPGA (not shown). The stack-up shown in Figure 4 is used in this example. Layer 2 (shown in green) is the ground reference for the 8-mil wide 100Ω differential trace that goes to the output pins SDO+ and SDO- of the LMH0384, as well as the LVDS signal routings for the LMH0340 and LMH0341. An island of metal on layer 4 (shown in blue) is used as the ground plane for the 75Ω traces. The two ground references are stitched together using the ground via for the device's DAP connection.

The AC coupling capacitor C2 is placed closest to the input pin at SDI+. The impedance matching network L1 and R1 are placed as close as possible to the input pin SDI+ through C2. The 75Ω termination resistor R2 is placed after C2 to minimize the effect of the stud.

This design uses 0402-size components to minimize the impedance change to the 75Ω trace built with 20-mil microstrip referenced to layer 4. The footprint used for the BNC should have good signal launch for achieving good return loss.

Figure 9. Layout Example for the LMH0384, LMH0340 and LMH0341 (click on image to enlarge).