Bangalore, India: Three researchers from a Saudi Arabian university and one from an Indian university have presented a basic strategy they say helps in creating a more efficient framework for processor verification. Too many things are taken for granted during the verification process, and while many of the steps are based on commonsense, they certainly need to be documented properly, they said, making this the cornerstone of their paper.

At a paper presented at the recent VLSI Design and Test forum in India, Asheesh Shah, Abdulaziz Mazyad and Hamed Elsimary from King Saud University, Saudi Arabia, and Ashwani Ramani from Devi Ahilya Vishwavidhyalaya, Indore, said that though formal verification is growing in importance, its integration with existing methodologies such as simulation and other verification modules is not very clear and remain vendor specific.

They framework they propose is based on commonsense as much as it is on identifying and covering all aspects of the verification process.

"The sophistication of recent processor architectures requires major logic verification effort both in terms of time and manpower. This is become a major bottleneck in overall time-to-market of the final product. Verifying the processor requires thorough test plans, efficient simulation technology and a proper execution plan. Further, verification challenges are created due to cache coherency, memory management and other subtle architecture design and features which can be vendor specific. Beside verification of the design, it is also necessary to test the performance of the newly designed chip. Both these tasks require large man hours and millions of investment," they said.

Clearly, some common features all processors will need are multiple processor cores for each chip, superscalar and out of order execution, aggressive pre-fetching of instruction and data, speculative execution, multi-level cache, IEEE compliant floating point execution unit, multithreading for each chip and dynamic power management.

The strategy the researchers propose is general, work-in-progress and has its limitations. Simulation largely serves as the main engine of all verification flows and formal and semi-formal methods complement the simulation-linked verification process. But they are constrained by design complexity and so cannot be applied across the core design.

With rising processor complexity, verification will face the challenges of increased architectural state space, increased complexities, tool limitations and manpower training, coverage and analysis, less controllability and project management issues.

A common strategy that can be applied across the board is difficult but a proper verification strategy (plan) in place before the actual processor start is basic to successful verification. This strategy acts as a guideline in the form of a simple checklist or a more complex document highlighting the flow and tasks. The complexities and work behind any industrial level verification process is indeed very large. And the reason that progress cannot be tracked very easily within the vast majority of verification processes is because the loop between implementation and the verification plan are made in a time consuming, error-prone, manual process, often done ad-hoc with data coming from various sources. This demonstrates the absolute need for the automated storage and analysis of verification data within the verification process, a robust strategy and a framework which can reduce bottlenecks if not guarantee complete cure.

"Verification projects can be managed and brought under control provided that the right combination of planning, data collection and measurement techniques are used - which calls for good project management techniques. Our strategy is nothing but a set of questions, goals and objectives along with some basic pre-requisities that we consider is necessarybefore any verification task starts. This is an essential and integral part of the process which helps in better decision-making and its importance will be clearly reflected in the outcome of the verification process. Many of these issues are taken for granted and can be termed as commonsense, but they still need to be documented," they said.

Pre-requisites

These are a proper choice of the tools (external or in-house) and their evaluation, keeping in mind reliability, scalability and time factors; identifying key tasks and highlighting dependencies to reduce the time the process takes; multiple models of each design unit at various abstraction levels; interface drivers and checkers in C/C++ monitors and debug tools; hand-generated test cases based on prior experience and, a team of verification engineers with good inter-personal communication skills.