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TechOnline India Miminizing Power Consumption in RTL Designs Using Sequential Clock Gating and Low-Power Synthesis By Venky Ramachandran EDA DesignLine (05/26/09, 09:42:00 AM EDT) The combined flow of automated, sequential RTL power optimization tightly linked to low-power synthesis provides designers with a highly efficient, single-pass, low-power design flow. An automated low-power design flow has been developed by Calypto Design Systems and Cadence Design Systems which combines the automated RTL clock gating of PowerPro CG from Calypto with the low-power synthesis of Encounter RTL Compiler from Cadence. Read the entire article here. 1

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