How to achieve 1 trillion floating-point operations per-second in an FPGA

by Michael Parker, Altera Corp. , TechOnline India - September 15, 2010

To date, virtually all FPGA-based signal processing has been implemented using fixed-point operations. This article describes how floating-point technology in FPGAs is not only practical today, but that the processing rates of one trillion floating-point operations per second (teraFLOPS) are feasible and can be implemented on a single FPGA die.

Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal processing has been implemented using fixed-point operations. This article describes how floating-point technology in FPGAs is not only practical today, but that the processing rates of one trillion floating-point operations per second (teraFLOPS) are feasible and can be implemented on a single FPGA die.

What’s changed?

Recently announced 28-nm FPGAs can enable much higher levels of both fixed- and floating-point digital signal processing (DSP) than ever before. A key aspect of this is the new and innovative variable-precision DSP architecture that efficiently supports both fixed- and floating-point implementations.

FPGA resources and architecture are by themselves are not sufficient to build floating point designs. Verilog and VHDL have poor to basically non-existent support for floating-point representation. There are no synthesis tools available today that support floating point. However, the traditional approach that is used in floating-point processors will not work with FPGAs. Therefore, a new “fused-datapath” toolflow has been designed to specifically build floating-point datapaths while taking into account the hardware implementation issues inherent in FPGAs. This design tool allows designers, for the first time, to create high-performance floating-point implementations of large FPGA designs.

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