PowerSoC solves switch-mode DCDC noise and space issues

by Michael Laflin, Enpirion, and Austin Lesea, Xilinx , TechOnline India - February 20, 2012

This article describes the various components of noise in a switch-mode DCDC converter and demonstrates how PowerSoCs can minimize those components. The article further shows design examples and demonstrates how PowerSoCs can power high speed IO with performance equivalent to or better than Linear Regulators.

Editor’s Note: This article appears in a somewhat shorter form in the Winter 2012 issue of Xcell Journal magazine (Click Here to see the article in this issue), and it is reproduced here in its expanded form with the kind permission of the folks at Xilinx.

Introduction

Conversion efficiency is driving FPGA system designers away from the use of linear regulators and toward the use of switch mode DCDC converters.  While switch-mode DCDCs offer dramatic increases in efficiency, they also require a much more complex design, increase part count and footprint, and most significantly for high-speed IO, switch-mode DCDC converters are a source of noise.

This article describes the various components of noise in a switch-mode DCDC converter and demonstrates how PowerSoCs can minimize those components.  The article further shows design examples and demonstrates how PowerSoCs can power high speed IO with performance equivalent to or better than Linear Regulators.

Simple model of a step-down DCDC converter

A very simple synchronous switch-mode DCDC converter consists of a pair of MOSFET switches, an inductor, and input and output filter capacitors. Figure 1 shows the converter during the switching cycle and its associated DC and AC current paths.  When SW1 is closed (SW2 open) current flows from the source though the inductor and to the load, the input and output filter capacitors “shunt’ the high frequency AC currents.  When SW2 is closed (SW1 open) energy stored in the inductor sources the current to the load through the second half of the switching cycle. The opening and closing of these switches and flow of the high frequency AC currents create noise.

 



Figure 1. Simplified synchronous step-down DCDC converter
during the full switching cycle.  The solid red line shows the
flow of “DC” currents while the dotted red line shows
the flow of high frequency AC current.

 

Key components of DCDC noise and mitigation strategies

A step-down DCDC converter effectively “chops up” a DC voltage into an AC voltage and then filters it back to a pseudo DC voltage.  This process introduces noise of four different types:

1. Ripple voltage on the converter DC output.
2. Ripple voltage on the converter input supply
3. Radiated EMI
4. Conducted EMI

 

Output Voltage Ripple

Every passive electrical component has besides its basic function (resistance, capacitance, inductance), a parasitic components of the other two: an equivalent series resistance (ESR) and an equivalent series inductance(ESL) in the case of a capacitor.  For a resistor, an equivalent series inductance and an equivalent parallel capacitance are present as well.

Output ripple is the by-product of the shunting off, or flow, of the AC ripple current through the output filter capacitor.  Figure 2 shows the small signal model of the output filter capacitor and the contribution each element of the model to the output ripple waveform.  Note that the ESL of the output filter capacitor combines with the parasitic inductance of the PCB traces return, and the internal parasitic inductance of the converter, to create the total ESL of the output filter loop.  The ESL creates the large high frequency spikes through inductive “ringing”.


Figure 2. Output voltage ripple components and sources.

Most DCDC converter supplier datasheets show low-pass filtered ripple waveforms and are thus generally unreliable as an indication of the actual ripple that would be measured on the PCB for a given application.

Mitigation Strategy: Fundamentally, to reduce output ripple one can either reduce the magnitude of the ripple current and/or reduce the ESR and ESL of the capacitor and the ESL of the PCB traces.  

Operating at higher switch frequencies will reduce the ripple current for a given inductor value and allows the use of smaller, lower ESR/ESL ceramic capacitors.  However, increased switch frequency increases switching losses in the MOSFET switches and will impact efficiency.

Placing multiple capacitors in parallel can reduce ESR/ESL in the same way placing resistors in parallel reduces their combined resistance. This is limited by the increase in PCB ESL with increasing capacitors and will increase the PCB real estate consumed by the converter.

PCB ESL can be reduced by using smaller sized filter components (inductor and capacitors) to reduce the length of PCB.  Unfortunately, the smaller inductor will generally result in higher ripple currents without increasing switching frequency.

The use of second stage filtering such as the use of a ferrite bead and capacitor between the DCDC output filter section and the target load.  The disadvantage of this approach is that the additional lossy element will affect regulation and could decrease efficiency.

Input Voltage Ripple

As the SW1 MOSFET opens and closes current flows from the source (VIN) with a near rectangular pulsed waveform.  The rise and fall times can be very fast, on the order of a very few nanoseconds.  

Much in the same way that the output ripple results from the ESR and ESL of the output filter capacitor and PCB trace ESL, the input ripple results from the input filter capacitor ESR and ESL, and the ESL of the supply PCB trace.  However, the magnitude of the input current ripple is much larger with large changes in current versus time (di/dt). Therefore the impact of PCB inductance is much more important and the input filter capacitor must tolerate higher RMS currents.  This high, fast switching current is also the primary source of conducted and radiated EMI to be discussed shortly.

Mitigation Strategy: As with the output filter capacitor, operating at a higher switching frequency allows the use of smaller, lower ESR/ESL ceramic input filter capacitors. The same cautions apply with regard to higher switching losses.

Minimize parasitic inductances in the input filter loop.  This is primarily accomplished by placing the filter capacitor as close to the DCDC as possible and making the PCB traces as short and wide as possible. The input filter capacitor should generally not be placed on the opposite side of the PCB and connected to the DCDC using vias.  This will introduce a large amount of inductance in the current loop.  

Radiated EMI

Radiated EMI results from the high, fast switching currents flowing through the input AC current loop.  Recall from your electromagnetic fields courses that the radiation efficiency of a loop antenna is a function of the loop radius relative to the radiation wavelength.

 

 

The equation shown above gives the power radiated by a loop antenna of radius r and wavelength lambda; n is a free space constant.  Note that there is a r8 relationship with loop radius while the wavelength has a: lambda4 relationship.  Hence there is a significant advantage in operating at higher frequencies if it allows you to use smaller components that result in a smaller input current loop radius.

Mitigation Strategy: Reduce the radius of the input AC current loop.  This can be achieved by switching at higher frequencies that enable the use of smaller ceramic filter capacitors.  The same caveat regarding higher switching frequency as listed previously applies; higher switch loss.

Conducted EMI

Conducted EMI comes from two primary sources.  The first is from the fast switching input currents being pulled from the input voltage rail which can cause both supply ripple (differential mode) and ground bounce (common mode) EMI.  The other significant source of conducted EMI results from the coupling of the inductor magnetic flux leakage onto PCB traces on the board.

Mitigation Strategy: Proper sizing of the input filter capacitor to supply or filter the high frequency AC currents to minimize the currents on the supply rail.

Minimize the parasitic inductance and ESL in the input AC current loop.  This can be achieved by operating at higher switching frequencies that enable the use of low ESL ceramic capacitors which in turn will enable a smaller loop radius. Once again, the same caveats apply with regard to higher switching frequency as switch loss.

Make PCB traces for the input filter capacitor as short and wide as possible to reduce trace inductance.

Use shielded inductors to reduce flux leakage.

PowerSoC as a strategy to mitigate noise

Enpirion introduced the world’s first PowerSoC in 2004.  PowerSoCs integrate the entire DCDC converter into a single IC package including the controller, gate drivers, MOSFET switches, high frequency decoupling, and most importantly the inductor.  Most PowerSoCs require only input and output filter capacitors so that the overall solution is simple and small.

Specialized deep sub-micron high frequency LDMOS is used to provide both low switching loss and to enable complete integration of control, drive, and switching elements.  The low switching loss makes high switching frequencies, typically 5MHz, possible.

High density, high permeability, low profile, magnetics are used to provide minimal AC loss with low DC resistance.  The low profile magnetics and magnetic structures exhibit self shielding properties that reduce flux leakage. The high switching frequency allows the inductor to be physically very small.

The high switching frequency enable the use of small input and output filter capacitors.  This in-turn makes the input and output AC loops very small reducing ripple and EMI.

The package layout is structured to further minimize the radius of the input and output AC filter loops and thus minimize radiated and conducted EMI and ripple.  

Package design includes RF techniques to minimize parasitic impedances within the internal circuit elements to keep high frequency AC currents contained inside the package.

PowerSoC results versus discrete implementation

Figures 36 provide a comparison between PowerSoC and discrete DCDC converter implementations.

 



Figure 3. Converter solution footprint comparison for a typical 4A case. The PowerSoC (left) has much smaller input and output AC current loops and is 1/7th the size of the typical discrete implementation. The dotted yellow rectangle demonstrates the size of the PowerSoC relative to the discrete DCDC.

 

 

 

Figure 4. Output ripple voltage comparison between PowerSoC (left) and discrete DCDC implementation (right). Ripple measured on vendor evaluation boards using same equipment and technique. Measurement bandwidth is 500MHz.




Figure 5. Radiated EMI measurements; CISPR22 Class B 3m. PowerSoC on left and discrete equivalent on right; measured on vendor evaluation boards.

 

 

 

 



Figure 6. Conducted emissions as measured at the input ground terminal.  

 

Application example powering Rocket IO using Enpirion PowerSoC

A daughter card was designed and built to plug onto a Virtex 5 development board (Figure 7).  Jitter measurements were made with both the Enpirion devices power the development board and with linear regulators.  Measurements were made with and without second stage filtering on the Enpirion PowerSoCs.  Table 1 shows the tabulated jitter results.

 

 

Table 1. Measured Jitter for Rocket IO.

 

 

 

 



Figure 7. Daughter card with Enpirion PowerSoC devices.

 

Conclusion

PowerSoCs represent a powerful new tool for the FPGA designer.  The devices significantly reduce the many issues encountered when changing over from linear regulator based voltage converters to the more efficient switch-mode converters.  PowerSoCs offer similar footprints and ease of design as linear regulators, while providing switch-mode converter efficiencies without the noise and complexity of a discrete converter implementation.

About the authors:

Michael G. Laflin is Director of Marketing at Enpirion, Inc. Michael may be contacted by email at mlaflin@enpirion.com

Austin Lesea is a Principal Engineer at Xilinx, Inc. Austin may be contacted by email at Austin.Lesea@xilinx.com

 

Article Courtesy: Programmable Lgic DesignLine

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