Circuit verification challenges in physical verification

by Kiran Joseph, Mentor Graphics , TechOnline India - February 02, 2012

Designers want a programmable solution in the physical verification space that performs advanced ERC/ESD checks and execute selected design rule checks. One that is applicable to multiple process nodes and easily usable across design communities is ideal.

Introduction

During physical verification, designers must ensure that their designs are fundamentally manufacturable. Using design rule checking (DRC), they determine if the spacing and widths of the polygons that were drawn are correct, and whether or not the layout can be printed. Similarly, using layout vs. schematic (LVS) they verify that the drawn layout matches the intended source netlist. 

Electrical rule checking (ERC) and electrostatic discharge (ESD) analysis enable designers to examine the functionality of the circuit, determine if there are any invalid paths in the design, and confirm the presence of ESD protection circuits that protect the design when an ESD event occurs. There are several techniques used to identify ERC/ESD problems in designs. A designer can perform manual (visual) checking, run dynamic/static simulations, or use schematic checking tools or TCL/Perl scripts to pinpoint potential problems.

However, designers are looking for a programmable solution in the physical verification space—one that would perform advanced ERC/ESD checks, as well as execute selected design rule checks. An ideal solution would be one that is applicable to multiple process nodes, and is easily usable across design communities.

ESD in Physical Verification

ESD is becoming an increasingly complex problem as scaling intensifies in integrated circuits (ICs). Technology scaling means the supply voltages, channel lengths, junction depths, and gate-oxide thickness are all reduced. With this trend toward miniaturization, the risk of IC malfunction due to ESD is on the rise. Some of the reasons for failure are: 

• lack of or wrong selection of protection circuits, 
• non-optimal metal connections, 
• improper protection of circuit connections, 
• incorrect bus layout, 
• non-intentional layout errors, 
• activation of parasitic devices.

Also, with the increase in the number of power supplies in the chip, multiple ESD buses are used to configure the whole-chip ESD protection scheme, further complicating ESD verification.

It’s perplexing that despite ESD failures contributing to 50% of all chip failures [1], adequate attention is still not given to ESD verification. ESD protection circuits can be located inside the pads, or they can be placed throughout the chip, depending on the package types (e.g., wire-bond or flip-chip). Because of this, different ESD verification methodologies must be adopted to ensure adequate protection in either case. In addition, ESD events governed by different ESD standards, such as human body model (HBM), charged device model (CDM), or machine model (MM), need to be separately verified. Just to further complicate the issue, overdoing ESD protection schemes may also impact the circuit performance, as they can cause circuit interference.

With the drive to achieve higher chip densities, many fatal mistakes are often committed by the designers that are only realized after the chip fabrication. On the one hand, implementing many such ESD verification steps may use up too much of the “time to market,” schedule; on the other hand, such cases can lead to failures if unchecked.

ESD protection schemes and verification methodologies

In the circuitry shown in Figure 1, a positive ESD voltage is applied to some input pin, with some output pin relatively grounded while the Vdd and Vss pins are floating. The ESD current will be diverted from the input pad to the floating VDD power line through the forward-biased diode in the input ESD protection circuit.

 

Figure 1. Power Rail ESD clamp configuration

 

The figure shows two possible paths for ESD discharge. The ESD current flowing in the Vdd power line can be conducted into the internal circuits through the connection of the Vdd line. If the ESD current is discharged through the internal circuits, it may cause damage to the internal circuits, as indicated by the Path 2 (red) current. If there is an effective ESD clamp circuit across the Vdd and Vss power lines, the ESD current can be discharged through the Path 1 (green) current.

In Path 1, the internal circuits are safely protected against ESD damages, because the shunting clamp protects the sensitive elements in the device by clamping the voltage developed during the event, and diverting the current away from the core circuit.

A clamp cell is an ESD protection device that is turned on only during the ESD event, providing a low-resistance path for discharge. The effectiveness of the clamp depends on the relative placement of the clamp cell, and its ability to respond quickly to the sudden discharge. The impact of clamp placement can essentially be captured using resistance.

The topology of a clamp cell can vary from a static clamp (like ggNMOS) to a transient clamp involving a detection circuit, delay element, and wide clamping transistors. The properties of such devices/elements are based on simulation or other estimation methods, and must later be verified against the properties actually present in the device. Identification of the components of the protection device at SoC-level is itself an important aspect of ESD verification.

An automated ESD verification method must be able to perform different kinds of checks for core and IO regions. Merely checking some pre-programmed checks, such as clamp-to-clamp or bump-to-clamp resistance checks, may not be useful in all cases. For example, in a wirebond chip, you need to evaluate the resistance of certain paths in the I/O ring, or some other points of interest inside the chip. As shown in Figure 2, one common check of specific interest from an HBM standpoint involves finding the resistance between consecutive supply pads in an I/O ring, then comparing this value against a user-specified threshold.

 

Figure 2. Programmable resistance checks

 

There also need to be verification methods that identify the presence of and perform both quantitative and qualitative assessment of ESD buffers/protection circuits at specific regions inside the design from a CDM perspective. Electromigration (EM) effects in ESD paths affect the properties of the wire, leading to ESD failures that may be catastrophic in nature, or occur over a period of time.

Paths like I/O-pin to bump or bond-pad to I/O may not be properly exercised in a simulation, meaning connectivity issues or undersized straps in such loops may fly under the radar and result in ESD failures post-tapeout. Such paths may need to be analyzed for EM failures from an ESD perspective. It may be impractical to do SoC-level ESD simulation to verify all these protection schemes — hence, a comprehensive verification method is essential.

One of the intricacies of ESD verification is ensuring that ESD circuits are appropriate to protect a certain topology of the circuit that is being protected. Part of this methodology requires confirming that no ESD protection circuit is incorrectly connected, which would degrade the performance of the circuit. For example, having a forward-biased diode between the power/ground network instead of a reverse-biased connection would result in a failure.

For an analog/mixed-signal (AMS) block, the ESD verification criteria may be very different. As illustrated in Figure 3, designers may be interested in determining the individual resistance of multiple discharge paths, such as pad-to-ground (Path 1) and ground-to-pad (Path 2), because the absence of anti-parallel diodes in certain topologies (e.g., Path 1) would cause ESD protection paths to break. Designers may also be interested in other reliability concerns, like verifying the presence and attributes of guard-rings need to provide latch-up protection.

 

Figure 3. Bi-directional diode to overcome ESD damage

 

Similarly, having erroneous connections in such circuits (e.g., parallel diodes) can obstruct the normal operation of the protection structure. A programmable ERC tool should allow designers to define such illegal topologies in a SPICE-like syntax, to enable the tool to automatically locate any occurrences. Figure 4 shows an anti-parallel diode protection circuit check defined by the user, which should be applied at nodes where ground domains are crossed.

 

 

Figure 4. SPICE pattern defining an anti-parallel diode check

 

Often, there are numerous design rules that must be verified to ensure that devices work as expected. Driver contention events happen if there are two logic gates from the same type that are connected to the same output, but have different inputs. Fan-out of various cells (like buffers) must be checked against user-specified constraints. A methodology to capture such conditions would be highly desirable, particularly if the method read inputs from all stages of the design cycle, from the schematic netlist to the layout GDS, so that various ESD problems could be identified and corrected regardless of where they occur, ensuring successful tapeout.

Calibre PERC (programmable electrical rule checking) is a tool from Mentor Graphics that allows designers to write their own electrical rules, particularly those who perform extensive ESD and ERC verification. Calibre PERC replaces manual or customer in-house solutions, which (in general) are error-prone, as well as simulation-based approaches, which aren’t very practical from an SoC perspective, as they may run for days.

Verification using this flow requires two inputs: netlist or GDS, and a Calibre PERC ESD rule deck. The netlist/GDS can be a schematic netlist, or a netlist extracted from the layout, or a layout GDS. In the case of the GDS, the LVS-like runset used for extraction must ensure that all ESD protection devices are extracted.

 

 

Figure 5. Calibre PERC process flow


In addition to ESD checks, Calibre PERC can perform voltage propagation checks, geometrical checks, multi-power domain crossing checks, and design rule guideline checks.

Voltage Propagation Checks

Static electrical voltage checks can be used to detect over-voltage conditions that can lead to device damage and circuit malfunction. Voltage propagation enables circuit characteristics such as voltage to propagate through the entire design without requiring vectors or transient simulation methodologies. Some of the conditions voltage propagation can be used to detect are:

• over-voltage conditions that can lead to device damage and circuit malfunction
• reverse current issues in high voltage ERC
• electrical floating gates/nodes
• voltage troubles at the interface of different domains
• maximum voltage across the gate oxides
• MOS pn junctions that are forward-biased

In the vector-less approach, voltages are defined for supplies using an approximation method where a node would normally see a voltage or a voltage range, and checks are generally based on max/min propagated voltages values (worst case condition). In the vector approach, voltages are defined for supplies and I/O pads using an accurate method where a node can normally see a voltage, and these checks are generally based on well-defined propagated voltage values. Figure 6 shows how the voltage propagation method can identify devices that have paths between various power domains.

 

Figure 6. Voltage propagation check

 

 

Topology-based geometrical checking

From a topological perspective, designers can create a simple Calibre PERC rule to identify the topology in the circuit. Calibre PERC uses the same rule to identify the circuit irrespective of whether the design is hierarchical or flat, and compares it to what it was intended to be. Geometrical checking is an extension of topology-based checking.

For example, if designers want to compare the OD layer extension for the device pair of the current mirror, they can first search for the topology of interest, then perform the geometrical DRC check, and lastly compare the result to a constraint to ensure that the spacing or extensions are identical for devices in all such topologies. With Calibre PERC’s DRC-style geometrical checking, designers can solve some of the most difficult DRC rule checks in a more elegant manner, and code rule checks that previously were difficult to code.

With Calibre PERC, designers can ask the more profound question—is this structure the one that I intended? Can it do the job? Many ESD protection circuits use 2 or 3 diodes connected end-to-end as a diode string. If the schematic was drawn incorrectly, the layout will also contain the same error. If designers simulate that net, they are probably going to find that the voltage drop over their diodes is not what they expected. Calibre PERC can help designers locate these hard-to-find errors efficiently and effectively.

Layout-Based Challenges

Changing focus from circuit topologies to layouts, Calibre PERC enables designers to perform a rich set of layout-based verifications, all of which are fully programmable, that can identify many issues. Some key examples of layout-based checks that have been implemented include: hot gate or diffusion checks, verifying design symmetry, and decoupling capacitor placements.

While a typical design rule check can treat all transistors equally to obtain these measurements, being selective about performing such checks, and having different rules for different device types has typically been a challenging proposition. With Calibre PERC, designers simply perform selected DRC checks for each identified device, with no new recognition layers required.

There are, of course, probably hundreds of other subtle (and maybe not-so-subtle) checks that designers would like to perform on their IC designs that they’re not able to do today, as well as an opportunity to improve some of the checks they’re already doing. Looking at some of those capabilities in detail, like the topological, current density, point-to-point, and DRC checking capabilities, it becomes easy to see how these checks can also be mapped to custom solutions.

Conclusion

As nodes decrease, design complexity increases, and tapeout schedules tighten, circuit verification, particularly ESD/ERC checks, becomes increasingly difficult and crucial to chip success. With the capabilities of Calibre PERC and the programmable nature of Calibre PERC rules, designers can search precisely for circuits and devices (with accompanying values) in a repeatable and deterministic manner. This flexibility is critical to providing each customer with a powerful customizable tool that is capable of solving their specific issues. Calibre PERC allows you to explore solution spaces that were previously problematic or tedious to code, while using a Calibre rule deck that can be employed for multiple designs.

References

1)      Sheth, Amit. “E.S.D ELECTRO-STATIC DISCHARGE.” Short Circuit 1, no. 2 (Nov-Dec 1998): http://ewh.ieee.org/r10/bombay/news2/story11.htm 

For more information, visit the Calibre PERC product page at http://go.mentor.com/calibre-perc 

 
About the Author:

Kiran Joseph is a Field Applications Engineer for Physical Verification with Mentor Graphics, working primarily with the Calibre product line. Before joining Mentor Graphics, he worked for Apache Design and NXP Semiconductor. Kiran received a B.Tech. in Electronics & Communication from Cochin University of Science and Technology, and a M.Tech in VLSI Design from the Indian Institute of Technology, Delhi. He may be reached at kiran_joseph@mentor.com.

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