Linear announces very low power 12-/14-bit 25Msps-125Msps ADCs operate at less than 100mW at 125Msps

by K C Krishnadas, TechOnline India - March 31, 2011

Linear introduces a family of ultralow power 14-bit and 12-bit, 25Msps to 125Msps analog-to-digital converters (ADCs) that dissipate less than 1mW per mega sample per second from a 1.8V supply, making them the lowest power high speed ADCs on the market

Linear Technology has announced a family of ultralow power 14-bit and 12-bit, 25Msps to 125Msps analog-to-digital converters (ADCs) that dissipate less than 1mW per mega sample per second from a 1.8V supply, making them the lowest power high speed ADCs on the market.

The LTC2145 family includes two-channel simultaneous sampling, parallel output ADCs,  offering a choice of full-rate CMOS, or double data rate (DDR) CMOS or DDR LVDS digital outputs with programmable digital output timing, programmable LVDS output current and optional LVDS output termination. 

At 25Msps, the 14-bit and 12-bit versions of the LTC2140 consume just 24mW per channel, while the 125Msps LTC2145 consumes only 95mW per channel. While claiming the lowest power dissipation, AC performance has not been compromised. At 14-bits, these devices achieve over 73.2dB SNR performance with 90dB of SFDR at baseband.

At 12-bits, the SNR performance is better than 70.6dB. This ADC family offers a pin-compatible upgrade path to the ultralow power LTC2185 16-bit ADC family to provide a 3dB performance upgrade while maintaining portability in such applications as handheld test and instrumentation, radar/LIDAR, medical imaging, PET/SPECT scanners, military radios, smart antenna systems and a range of low-power communication systems. 

Pin-compatible speed grade options include 25Msps (24mW/ch), 40Msps (33mW/ch), 65Msps (46mW/ch), 80Msps (55mW/ch), 105Msps (75mW/ch) and 125Msps (95mW/ch). Additional power savings can be achieved by placing the devices in standby (16mW) or shutdown (1mW). Analog full power bandwidth of 750MHz and ultralow jitter of 0.08psRMS allows undersampling of IF frequencies with excellent noise performance. These devices incorporate Linear Technology’s digital output randomizer and alternate bit polarity (ABP) mode feature for reduced digital feedback.

Available in compact 9mm x 9mm QFN packages, designers can benefit from the flexible choice of interfaces that minimize pin count and ease routing to FPGAs. These ADCs will be available in production quantities beginning in May through June 2011, with demonstration boards and samples immediately available through your local Linear sales office. Pricing starts at $10.95 each for the dual 12-bit 25Msps devices in 1,000-piece quantities. The complete product family can be found at: www.linear.com/HSADC  
 
Summary of Features: LTC2145
 
* 12-/14-Bit, 25Msps-125Msps ADCs
* 73.2dB SNR, 90dB SFDR (14-bits 125Msps)
* Low Power: 95mW/Ch at 125Msps
* Single 1.8V Supply
* Flexible Digital Interfaces: CMOS, DDR CMOS or DDR LVDS Outputs
* Selectable Input Ranges: 1VP-P to 2VP-P
* 750MHz Full-Power Bandwidth S/H
* Optional Data Output Randomizer
* Optional Clock Duty Cycle Stabilizer
* Shutdown & Nap Modes
* Serial SPI Port for Configuration
* 64-Pin (9mm x 9mm) QFN Package 
 
 
 

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