Study gives mixed marks to high-level synthesis

TechOnline India - January 18, 2010

High-level synthesis tools for FPGA design deliver excellent results and are very usable, but do not fully abstract users from the FPGA RTL flow, according to a study conducted by benchmarking and analysis firm BDTI.

SAN FRANCISCO—High-level synthesis (HLS) tools for FPGA design deliver excellent results and are easy to use, but do not fully abstract users from the FPGA RTL tool flow, according to a study conducted by benchmarking and analysis firm BDTI Inc.

In the study, created with help from FPGA vendor Xilinx Inc., BDTI engineers using HLS tools with an FPGA achieved results equal to an FPGA designed with RTL and 30 times better than a DSP processor, according to the firm said.

But weaknesses in RTL tools prevent HLS tools from fully delivering on their promise, because HLS tools only accelerate a portion of the design flow, BDTI said. After generating RTL code using HLS tools, users still need an experienced FPGA designer to implement the code at the back end using FPGA design tools, the study found.

Preliminary results for the BDTI Optical Flow Workload, as judged by maximum frame rate achievable at 720p resolution (source: BDTI).

"High-level synthesis tools did a great job getting us from C to RTL, but once we are at the RTL point we had to take that RTL in a manual way through the traditional FPGA tool flow," said Jeff Bier, founder and president of BDTI. "Getting from RTL to a bit stream on the FPGA required a lot of expertise."

HLS tools have been around for roughly 20 years, mainly for ASIC design, but have not enjoyed large-scale success, BDTI noted. This has resulted in widespread skepticism that they will ever deliver, according to BDTI.

Bier said BDTI launched a program to evaluate HLS tools targeting FPGAs because processor users seeking high performance are being forced to move to multi-core chips, but parallel programming tools and techniques are immature. Also, many FPGA users are facing design-cost and time-to-market crises as designs get more complex because RTL design is difficult and time-consuming, Bier said. Making FPGAs much easier to use through HLS tools "could be a real game changer," Bier said.

So far, BDTI has evaluated only two HLS tools: AutoPilot from AutoESL Design Technologies Inc. (Cupertino, Calif.) and Pico from Synfora Inc. (Mountain View, Calif.). {pagebreak}Tom Hill, system generator product manager at Xilinx Inc., said Xilinx doesn't dispute BDTI's conclusion that HLS tools don't fully abstract the user from FPGA RTL flow. Xilinx' place-and-route environment is "pretty feature rich" to enable experienced hardware designers to get the last 10 percent out of a chip, he said. Xilinx is hopeful that customers will adopt HLS tools and that the HLS tool vendors work with Xilinx to address the limited integration between the tools and Xilinx RTL tools, Hill said. "We don't view this as something we can solve on our own," Hill said.

"What we really need to do is have a little bit more seamless integration between the Pico tool and the FPGA software. I think by working together we can make it pretty seamless," said Vinod Kathail, Synfora's founder and chief technology officer.

"If you wanted to have a flow that a TI DSP software programmer could pick up and use automatically, with today's flow you would run into difficulty," said Andrew Haines, vice president of marketing at Synfora. "[The flow] assumes that it's an RTL guy running those tools. The perfect solution is not realizable today."

Mentor Graphics Corp. and Forte Design Systems Inc. are the market leaders in HLS according to market research firm Gary Smith EDA. Bier said two other firms have licensed materials from BDTI to begin self-evaluations as a pre-cursor to participating in BDTI's evaluation of HLS tools. But Bier did not identify the other two companies, saying BDTI policy is to allow participants in its benchmarking studies to announce participation when they choose. Assuming the two other firms move forward with the evaluation, it will be several months at least before BDTI has data on their tools, Bier said.

Bier said market leaders tend to lag behind smaller firms in participating in benchmark studies. "Whenever you are introducing a new yardstick, typically the bigger, more established players are more wary of it, and the upstarts have the most to gain." Bigger firms often don't participate until smaller companies tout results and customers begin asking them about it, Bier said. {pagebreak}BDTI engineers used AutoPilot and Pico to design on a Xilinx Spartan-3A DSP 3400 for one video application and one wireless application. The results were compared against those achieved using a Texas Instruments Inc. TMS320DM6437 DaVinci video processor and TI development tools in the case of the video application and a Spartan-3A DSP 3400 in the case of the wireless application. More data on the benchmark study is expected to appear on BDTI's web site Monday (Jan. 18).

BDTI concluded that AutoPilot and Pico did a good job generating quality RTL implementations from user-modified C code. Though significant vendor support was required for ramp-up, both tools are very usable for hardware-aware DSP software engineers, BDTI said. HLS tools also required less code restructuring than the optimized DSP processor implementation. BDTI said.

Usability results based on BDTI's Optical Flow workload (source: BDTI).

The cost of HLS tools is relatively small compared with traditional ASIC design tools, but expensive compared with standard FPGA design tools are DSP development tools, Bier said. "For some users that's going to be an obstacle," he said.

But Bier said that in some cases HSL tools may enable companies to bring products to market or hit market windows that they wouldn't otherwise, which would justify the costs. Bier said he believed the HLS tools evaluated cost less than $100,000.

Usability results based on BDTI's Optical Flow workload (source: BDTI).

BDTI surveys revealed that there remains wide-spread skepticism among users about HLS tools because they've been around for 20 years without catching on in a big way, Bier said. He added that earlier generations of HLS tools were oversold—they couldn't do what vendors said they could.

"An additional factor, I think, is fear," Bier said. "Engineers fear being replaced by HLS tools. The reality is that you still need a very skilled engineer to operate the tool effectively, and to take the output RTL the rest of the way to implementation." But BDTI also spoke with many high-end companies that are using HLS tools and getting good results, Bier said, which prompted BDTI to study the issue further.

Synfora's Haines said HLS adoption remains at "quite an early stage." But both he and Bier said it is no longer un-measurably small The combined totals of what all HLS vendors are selling is now into the tens of millions of dollars, Bier said.

Haines said the HLS adoption curve is starting for real and that the tools have real deployments and successes. "The number of designs that can be addressed by the tools is real," he added.

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