The integration of analog with digital and the increase number of on-chip features in mixed-signal controllers demand more complex I/O structures. Though they are sometimes some of the most neglected features of a chip, I/O (Input / Output pins) can represent a great deal of functionality in a SoC (System on Chip).
The I/O structure in today’s SoC is so feature-rich that a full understanding of their capabilities is important to understanding how to do more effective system design, and achieving greater value from the SoC.
In this two part article, we will discuss the following:
* basic understanding of the structure of an I/O block in any digital device
* different specifications of pin, which need to be understood, while selecting the device for application
* different variants of configurations of I/O block which need to be used for different application requirements* choosing the particular configuration that will achieve both reduced BOM cost and improved system performance
Drive mode is the way the pin is driven based on its output/input state. In this section we will look at some of the drive modes generally used in a generic System on Chip. When it comes to drive modes, it is mainly about digital, as high impedance is the only drive mode used for analog apart from some exceptions. These drive modes can be named differently by different SoC manufacturers but can be recognized easily by looking at their I/O architecture. If these drive modes are used appropriately, it will help to yield better system integration and reduce BOM cost. Let us look at the very basic output stage of an I/O cell.
Basic digital output cell: As shown below in Figure 1 below, the output driver available in most of the controllers. This drive mode may be known as strong or CMOS drive mode in different controllers.
If we look at it closely, it is nothing but the inverter which has its input controlled by a register bit generally called the data register in. (The reason it is called strong is that the CMOS inverter drives both ‘1’ and ‘0’ at strong levels).
All other drive modes are nothing but slight variation of this CMOS inverter to achieve different system topologies. Let us look into these variations.
Resistive Pull up/Down: This drive mode helps to reduce BOM in most of the applications so we are discussing it at first. In resistive pull up/ pull down mode, a resistance is introduced between the drain of MOS transistors and pin pad (Figure 2 below).
Figure 2: Resistive Pull up/ Pull down drive mode
So, it limits the current flowing through the pin and serves the same purpose as any other external pull up/ pull down resistance does. In applications, where a switch needs to be interfaced, a pull up / pull down resistance is needed to keep the input at a defined logic.
This pulling up/down of the pin can provide a stable default state and thus avoid random fluctuation that could occur due to noise. Now, the resistance internal to GPIO cell can be used for this purpose in a resistive pull up/ down mode. (Figure 3 below).
Figure 3: Use of internal pull up resistance to interface switch
Also, there are cases in communication protocols where the pins act as bidirectional interfaces. In such an instance we tend to use external pull up/ pull down resistors.
One point worth to be noted is, generally these internal resistances are very inaccurate. So, they cannot be used in case precision is one of requirement.
Open drain modes: The open drain mode is the case where one output state of the pin activates its corresponding transistor but the complimentary state is a high Z. For example in case of open drain drives low drive mode, the pin is driven strong low when data register bit for the pin is ‘0’ and it is high Z when the data
register bit is ‘1’.
This mode is useful when used in communication protocols like I2C where the pins have a bidirectional nature. This would be achieved by having an open drain mode with an external pull up resistor. Thus in the high state of the pin it is waiting for activity from the other side of the line. Figure 4 below shows the drive structure for the Open drain modes.
Figure 4: Open drain drive modes
Usage mentioned above is the standard use case for open drain drive mode. But there are so many other functionalities that can be implemented using this drive mode.
For example, recently we used this drive mode to replace one analog switch. Yes an analog switch! In this application, a capacitor needed to be charged with an IDAC and then after a fixed amount of time, discharged to ground.
The IDAC connects to the capacitor through a pin on the device which is configured for an open drain drive low with a value of one written to its data register. This meant that the pin was treated as a high impedance, which is ideal for analog signals.
The discharge required the capacitor to be connected to ground. This was
achieved by writing a zero into the data register of the pin. Simultaneously, disabling the IDAC avoided current flowing into the pin grounds.
Another advantage of using this implementation is lesser discharge path resistance as no analog switches are involved apart from one NMOS transistor.
High impedance mode: This mode is generally used as an input drive mode for the pin. In this mode the output drive circuitry of the pin is disabled. Many controllers like the Cypress PSoC3/5 use this mode in a digital and analog perspective. In a digital perspective the pin drives an input threshold Schmitt
trigger to drive some internal digital circuitry. After this, the signal (Digital now) changes the state of a pin state register. In some of the devices like PSoC3/5 which have a programmable digital structure implemented inside the device, the same digital signal is then routed into the digital routing structure.
When the pin is used to bring as an analog interface it is still maintained in a High impedance state since you don’t want any kind of output drives on it. But an internal routing architecture might take care of getting the analog signals to their destinations. This is normally achieved by the use of internal analog switches in
the device which can switch internal analog signals onto the pin.
Devices like the PSoC3/5 have a versatile analog architecture implementing multiple analog components like ADCs and Opamps internal to the device. The signals into or out of such blocks require to come to pins with high impedance drive mode.
Drive strength & driving higher current loads
Another major factor a designer should consider while designing a circuit is the case where his outputs are driving loads. Many a time a digital output might be used to drive a component like an LED or even drive other loads that actuate another mechanism.
In these cases it is very important to understand the drive strength of the pin driving the output circuitry. For example if the pins were driving LEDs that take up a load current of 20mA, then the pins should be able to support this load requirement.
In cases where a single pin cannot support this huge current requirement; the user can gang multiple pins together to provide a cumulative current capability.
So, it is not always needed to use external drives to support current more than the specified current for a single GPIO as long as enough pins are available to give cumulative current as per requirements.
In some devices the maximum sink current for the pin would be higher than the max source current. In such circumstances the user can make efficient design for the LED circuitry to sink current than to source it. Thus the advantage of having a higher sink current is utilized by the design.
Slew rate and its effects
Slew rate is one of the most important parameter to be looked at. Slew rate defines the rise time and fall time of the digital output. High slew rate results in fast rise and fall times and on the other hand slow slew rate does the opposite.
In GPIOs, slew rate is reduced by changing the RC time constant of the input of CMOS inverter (a series resistance is inserted between the invertors used for inversion and actual output driver).
The drive circuit shown in Figure 1 possesses the high slew rate while the one shown in Figure 5 below possesses the slow slew rate.
Now the question is, which one to use when?. To determine this, let us look into the advantages and disadvantages of each.
Fast slew rate: Due to fast rise time and fall time, output contains high frequency components. It leads to two major issues. First is electromagnetic interference (EMI) and second is interference with other signals on the board. High frequency components get radiated even with small trace length (required antenna length is
proportional to wavelength of signal).
So, if a high slew rate is used, it may create EMI issues in the design. High slew rate signals tend to get coupled on adjacent traces and create issues especially with analog signals.
There is a parasitic capacitance between traces. As shown in Equation 1, below, if we look at the impedance of capacitor, it is inversely proportional to the frequency.
In this equation, f is the frequency and C is value of capacitor. So, at high frequency coupling is increased between traces due to a low impedance path.
Slow slew rate: Generally, to increase the rise time and fall time, input to the CMOS inverter is slowed down using the series resistance as shown in Figure 5 below.
Opposed to high slew rate, slow slew rate is least prone to EMI and inter-trace coupling. The only disadvantage of slow slew rate is higher power consumption. The NMOS transistor will operate in saturation as per Equation 2 below.
The PMOS transistor will operate in saturation as per Equation 3 below.
Where VDS is drain to source voltage, VGS is gate to source voltage and VT0 is threshold voltage of the transistor. Figure 6 below shows the VTC (Voltage Transfer Curve) characteristics of CMOS inverter.
Figure 6: Voltage transfer curve of CMOS inverter
As can be seen from Figure 6 above, when Vin is about Vdd/2 both NMOS and PMOS are in saturation. When both transistors are in saturation, very high current flows between supply rail and ground through these transistors.
(Note: This figure is just an example. The transfer curve can move to left or right based upon transistor sizing and voltages on x and y axis depends upon the Vio).
Also, current is high when one transistor is in saturation and another one in linear. Due to slow charging and discharging of gate capacitance at inverter input in slow slew mode, both transistors conduct at the same time for longer period of time whenever output switches. Hence effective power consumption increases.
Based upon the application, slew rate can be selected. Slow slew rate can be the best option if power consumption is not the highest priority. However, in high frequency communication, high slew rate is the only option.
When forced to use high slew rate, you can avoid EMI by following good layout practices like having the return paths of the signal to be underneath (if possible) or right next to the signal traces.
ESD Protection diodes
Most of controllers/SoCs have electrostatic discharge (ESD) protection diodes on the pins to protect device from electrostatic discharge. This specification must be checked carefully.
Based upon the ESD at the place where product will be deployed, it needs to be made sure that pin’s internal diode can withstand a particularly high voltage for a particular amount of time.
There are different ESD models like industrial model and Human body model. One should make sure that these specs are met. If internal diodes are not capable to handle the required ESD, external diodes must be used. So, while selecting an SoC, one should make sure that pins have ESD protection.
ESD diodes, not only protect the device from ESD, but also adds constraints on voltage applied on the pins. This is why powering the IOs before powering the device is considered damaging.
When device is not powered by the power pins and voltage is connected to IO pins, device is back powered from the pin through the ESD diodes. It can damage the IO cell due to excessive currents flowing through it.
Another question which we quite often get is, can we connect more than rated voltage to IO input? Answer depends upon the spec of the device being used.
(This voltage must not be confused with ESD voltage rating. ESD voltage rating is based upon the particular model which defines the amount of time for which high voltage can be applied).
The first point to be looked at is, maximum operating voltage of device. The input voltage – forward voltage of the diode must not go beyond the maximum operating voltage of the device.
Another point to be considered is the maximum forward current of ESD diode. If the input voltage causes current higher than this current, an appropriate value of series resistance must be used to limit it.
Though these workarounds can be used, they are not very safe to be used. The second part of this article discusses about capabilities of some devices which allow different pins to have different Vdd supply.
Having dealt in Part 1 with some of the basics of SoC I/O pin assignment, in this second part we will deal with a variety of implementation issues, including hot
swap, threshold voltages, interrupts, pin assignments and Interfacing with the devices being operated at voltage other than SoC’s core voltage.
Systems like industrial and network equipment requires live insertion or hot swap to avoid long start-up operation or other down time related inconveniences. Hot Swap usually means that an electronic module can be removed and then reinserted into a system while the system remains under power. The assumption is that the removal of the module and reinsertion will cause no electrical harm to the system.
To deal with this scenario, the interconnecting IOs must have what is called hot swap capability. This basically means that IO pins must offer a high impedance drive mode even if the module is not powered.
Normal GPIOs generally come with a limitation that the voltage input on it cannot be greater than the Vdd of the device. This is due to the ESD diodes on the IOs which start conducting when the IOs are higher voltage than the Vdd, as discussed earlier.
Certain SOCs comes with special IOs which have an ability to Hot swap. These pins can connect to another system that is powered even when the device having the pins is not powered. The unpowered device can maintaina high impedance load to the external device while preventing itself from being powered through an IO pin’s protection diode.
In designs that would have a requirement to be part of a plug and play arrangement and requires a hot swap, the system designer should consider the case while part selection. The number of these hot swappable IOs required is another consideration the designer would have to look into because hot swap capability is available only few IO lines in device due to design overhead to implement them.
Input threshold voltage for any pin is characterized as the minimum input voltage that will be considered as logic High and maximum input voltage that will be considered as Low. Though most of the digital devices have CMOS drive level now a days, there are still many devices available which have other output levels like LVTTL (Low Voltage Transistor to Transistor Logic).
To deal with such I/O level mismatches, systems need the use of some interface devices that have selectable input threshold. To avoid the use of such external level translators, one must consider selecting an SoC/Controller which has i/o input threshold compatible with other devices.
Some of the SOCs have IOs that have programmable threshold where user is
not restricted to standard threshold voltages. Changing the threshold is nothing but changing the reference voltage to the hysteresis comparator. Based on this functionality these pins can now be considered as simple comparators. There might be cases in the design when this functionality can be helpful.
Interfacing at other than SoC core voltage
While designing any system, many a time embedded designers face the problem that one of the devices work on a 3.3V domain and the other works on the 5V and some time on some other non standard voltages as well. Now interfacing them so they can communicate becomes a concern in design. But there are some tricks by using the IOs redundant capabilities to achieve this.
Let us consider a case when one device (Device A) is working on a 5V supply and requires communicating with another device (Device B) that is working on a 3.3V supply. The setup is illustrated in Figure 7 below.
Now first device cannot drive the line using the 5V level due to the ESD protection diodes as discussed in first part of article. This is a case where we could employ level translators to interface the two voltage domains. But there can be a way to work around this problem by using the internal drive modes explained previously.
Open Drain Drives low mode can get the pin to go to 0v when its state is zero and High Z when it is 1. Now if we were to make a open drain drive low pin on the device powered to 5V and have it pulled up externally to a 3.3V supply what we achieve is the 5V device now signaling at a 3.3V level.
Figure 7: Interfacing two devices operating at different voltages
But one must keep two things in mind while using this solution:
1) If this pin is being used in bidirectional mode, pull up voltage must not be less than VIHmin of the receiving device. For example if device A has a higher operating voltage hand, its VIH can be about 2V and if pull voltage is 1.8V, input voltage may not be recognized as High though device B is trying to drive the line High.
2) There is a resistive pull up which effectively in series with the pin capacitance thus adding an RC time constant to the pins rise and fall time. Thus the pull up resistor causes a delay medium due to the RC network setup between the pull up resistor and the pin capacitance. This can cause longer rise/fall times on the signals on the pin.
Above mentioned method can be used in many systems as most of the SOCs
support open drain drive modes. However, they may be challenges while using this method due to the constrains described. Also, open drain drive modes need the use of external resistance which challenges system integration.
The best way to deal with this problem is to have different set of input output pins connected to different supply voltages as shown in Figure 8 below.
Some of the SoCs have their IO pins divided into several groups and each group can be operated at a different supply voltage. They eliminate the need of external voltage translators saving the board space and system cost.
One of the examples is Cypress’s PSoC3 and PSoC5. These devices have
concept of quadrant supplies where the IOs are separated in distinct 4 quadrants. Each quadrant can have independent IO supplies and all associated IOs will signal at this IO quadrant voltage.
Figure 8: Using separate supply for separate group of IOs
The solution mentioned above no doubt works well when there is need of four (4) supply voltages for large group of IOs. What if there are few IOs which need to operate at different voltage?
Some of the SoCs have hardware controlled VOH for the pins. This is generally to avoid the larger group to work at a particular voltage when only a few pins are needed to run at the voltage. In such pins, source of PMOS transistor can be connected to any drive voltage.
With controllable source voltage, programmable drive modes these pins can resemble as uncommitted NMOS transistor. A while ago, we were trying to implement an MDAC (Multiplying Digital to Analog Convertor) in a device which natively did not have any of those.
One may think why someone would talk about MDAC while talking about IOs.
But, capability of IOs to have hardware controlled VOH helped in implementing MDAC in that device. Figure 9 below shows the implementation of an MDAC with the help of IOs.
Figure 9: Using programmable VOH capability of the pins to implement a building block of MDAC
In this implementation, PWM’s duty cycle define the digital code. IOs helped to chop the PWM output between Input voltage and analog ground to implement the multiplication between digital code and input signal. Sign could be controlled using the Mixer available inside the chip.
Interrupts on input pins are used in any system to deal with and external event that requires triggering a code execution outside normal execution sequence. In basic controller based systems, most of the events contribute towards interrupt through input pins.
In case of SOC based systemsthe different peripherals in the system could contribute to interrupts to the design. But one of the most used interrupt source is still the IOs. Dealing with interrupts can be a significant overhead in some SoCs if number of interrupt lines are many and can cause system’s performance to degrade extensively.
So, one must understand interrupt handling on input pins while selecting the controller if input pin interrupt is an reasonable part of the system design.
Some controllers like the traditional 8051 tends to have one dedicated interrupt just for IOs. This means that the code execution on occurrence of an interrupt on any IO would transfer control to a specific interrupt vector. This is useful since there is a dedicated vector for IO interrupts.
But to distinguish which IO generated the interrupt would require the designer to add extra code in the interrupt to mask the inputs. However, it may be enough for some systems where interrupt is enabled only of very few lines or latency in servicing the interrupt is not a criterion of system performance.
Most controllers today tend to have a interrupt controller unit dedicated for the IOs. This architecture allows having a dedicated interrupt vector for each pin port. This is helpful since the interrupts are already vectored according to the ports from which they were generated.
The distinction in code needs to only mask the pins if required. In some applications, even there may be a need to resolve interrupt per pin and have a dedicated interrupt service subroutine for each of those.
So, to deal with such situation, some devices have capability of routing the pins to other digital peripherals and use their interrupt vectors.
There is another importance point to be taken care when it comes to interrupt on IO pins. Based upon requirement, one may need an interrupt to be triggered on rising edge or falling edge or on level.
There may be multiple requirements in the same system as well. Some of the devices available in market have capability to select interrupt type on pin basis. System designer must check these capabilities if needed in system.
We have seen about how IOs in today’s SOCs and controllers can be a mix of multiple functionalities. Where on the one hand SoCs empower user to integrate extensive features in single chip and encapsulate a gigantic system into a very small form factor, on the another hand they enforce user to bear some points in mind while assigning the pins for different functionalities.
Sometimes some IOs are configured as analog IOs where as others are just
digital interfaces. Some are high current drives while others are high precision inputs. Hence to extract most out of the features of configurability and adaptability of these IOs, the design should take at most care in pin selection and placement.
Consider a case of an application that was having an analog precision temperature sensor connected to an SOC’s analog input. If the same device was to drive a PWM that in turn drives an actuator like an LED or motor driver, then the effect of the PWM on the analog input has to be taken care of.
Care must be taken in such cases to ensure that the analog input is placed at the most farthest IO from the PWM. The farther these interfering IOs are the lesser the cross talk they would see and thus reducing the noise seen in the analog measurements.
Sometimes adding a ground trace on either side of a sensitive signal helps in reducing its susceptibility to noise. On a similar note, adding grounded IO pins on either side of a sensitive signal line can also shield it well against a pin to pin coupled noise.
As discussed earlier, there are devices which have separate supplies to offer a distinct operating voltage per IO group. Apart from serving the purpose of just having separate operating voltage, these type of IO architecture could also serve the purpose of better isolation between signals.
The sensitive analog signals could all be populated in a specific group while the other digital and drive signals could be on other group supplies. This effectively avoids any kind of power supply or ground noise that could have coupled through.
There are extensive specifications and features which an IO pin possesses and the
architecture of the IO block in SoCs/controllers has evolved with technology. IO pins available in advanced devices have capability of selecting a particular drive mode based upon the external entity device is talking to.
Selectable slew rates let user decide if they want to deal with EMI issues externally or want to control them on pin level itself. Pins have ESD protection diodes protects to protect the device from electrostatic discharge but impose a lot of changes while dealing with issues relating to hot plug and play and interfacing the devices operating at higher voltages.
Some IO architectures have IOs divided in to multiple groups so that they can be powered at different voltages. Where, some of the devices have this capability even on pin level. Overhead while IO interrupts can ruin system’s performance.
Some of the SoCs available in market have capability of resolving IO interrupt on pin basis. Embedded designers must understand the capabilities of IO and how the appropriate usage of them can make system compact, cost effective and efficient in terms of speed.
About the authors:
Sachin Gupta is a Senior Applications Engineer at Cypress Semiconductor. He enjoys working on different mixed signal applications. He can be reached at firstname.lastname@example.org.
Kannan Sadasivam is a Staff Applications Engineer with Cypress Semiconductor Corp. He has spent a considerable amount of his past career designing and integrating Satellite subsystems. He loves working on different types of analog circuits and applications. He can be reached at email@example.com.