Direct diagnosis for compressed ATPG patterns: A successful industrial experiment with layout-aware diagnosis

by Hu Sun, Wanggen Zhang and Thryambak Chandilya , TechOnline India - October 19, 2011

Advances in scan diagnosis technology such as direct diagnosis and layout-aware diagnosis have been shown to provide accurate and valuable results that reduce the failure analysis cycle time. In this article, we describe the detailed steps needed to set up a scan diagnosis flow and present our experimental results.

For several years, we have been producing a five-metal system-on-chip (SOC) design manufactured in a 0.18 µm process at a major foundry. Recently, we experienced a yield loss representing a 1% to 1.5% increase in failures found during manufacturing test. The root cause of yield loss was determined to be caused by a variation in the manufacturing process. The failure analysis (FA) engineers spent six weeks trying to find the suspected defect location, with no success.

As an experiment, scan diagnosis was introduced to the flow at the design site to support the FA engineers’ efforts. Identifying and localizing defects is crucial for ramping up and monitoring yield, especially when a new process technology is introduced. Although not already in use for this product, diagnosis is an established method used to identify and localize defects in digital semiconductor devices that fail manufacturing test. Advances in scan diagnosis technology such as direct diagnosis [1] and layout-aware diagnosis [2], have been shown to provide accurate and valuable results that reduce the FA cycle time. In this article, we describe the detailed steps needed to set up a scan diagnosis flow and present our experimental results.

Implementing manufacturing test compression and scan diagnosis

Scan test is a technique widely used for manufacturing test of digital semiconductor devices. Many integrated circuit (IC) designers leverage on-chip compression logic such as Mentor Graphics Embedded Deterministic Test (EDT) [3] to decrease test time while maintaining quality of test results. The EDT logic, which is embedded into the chip, includes decompressor and compactor logic connected to short internal scan chains. The decompressor logic decompresses the data from the input channels and loads the scan chains. The compactor logic compresses the scan chain outputs and connects these to the scan output channels.

Compared to a traditional scan architecture, which connects the long scan chains between the scan input and output channels, this architecture shortens the internal scan chain and therefore greatly reduces the scan shifting time. An important consideration for selecting a scan compression technology is the impact compression might have on diagnosis. For traditional scan patterns, a failure on a device pin directly corresponds to a failure on a specific scan cell. But with scan compression, this is no longer the case.

For some compression technologies, diagnosis can only be applied on dedicated patterns that bypass the compression circuitry. This makes the diagnosis process more cumbersome and makes it impossible to collect fail data for diagnosis during production test. However with EDT, the compressed patterns can be diagnosed directly, and dedicated patterns are not required [1].

The IC device that we used in this scan diagnosis experiment contains EDT logic. EDT reduces test time while maintaining the same test quality—160 internal scan chains are loaded by 8 external scan channels. This enables an effective 13X compression ratio compared to a traditional scan design.

Diagnosis flow

Certain requirements have to be understood and considered earlier during the design process to get the full benefit from scan diagnosis. Before there is a problem, ensure the flow for diagnosis is set up. If not considered early in the design process, the diagnosis process can be unnecessarily complex or even unfeasible. A typical diagnosis flow is shown in Figure 1.

 

 

 

Figure 1:  The direct diagnosis flow

Preparing the patterns and design netlist

The patterns needed for diagnosis are the final ATPG patterns, which should be fully verified through gate-level simulation before running on the tester. The design netlist needed for diagnosis is the same gate level netlist used for ATPG, as well as the potential constraints used to set up a specific test mode.

Preparing the failure log

The failure log from the automatic test equipment (ATE) usually contains the following information: the cycle each failure occurred, the signal on which each failure occurred, the expected value, and the actual value (Figure 2). The failure log must be provided in a format that the diagnosis tool can read.

 

Figure 2: J750 ATE failure log

Diagnosis products such as Mentor Graphics Tessent Diagnosis typically support both cycle-based and scan pattern-based formats.We preferred cycle-based format because of its similarity to ATE failure logs. We used a Perl script to convert the ATE failure logs from the Teradyne J750 tester to reduce the manual conversion time and improve the accuracy. A converted cycle-based failure file is shown in Figure 3, which corresponds to the ATE failure log in Figure 2. Special attention should be paid to the failure cycle number because the ATE cycle may not match the ATPG pattern cycle — if the ATE cycle starts from 1, the cycle number after format conversion should be ATE cycle minus 1, because the ATPG pattern cycle starts from 0.

 

Figure 3: Cycle-based failure file

Preparing for layout-aware diagnosis

A traditional logic-only diagnosis approach will only report the suspected net or cell name, which then must be manually located in the layout. Layout-aware diagnosis reports the suspected net or cell name and automatically finds the location in the layout. This type of diagnosis improves efficiency by reducing the suspected area based on the layout analysis. Layout-aware diagnosis requires two additional steps before loading the test pattern:

1. Check the consistency of all LEF/DEF files, compare the layout information contained in these files against the netlist, and save a compact representation of the layout.

2.  When running diagnosis, use the generated compact layout file. This automatically enables all layout-aware features and access to the layout information during the regular diagnosis and reporting.

Running diagnosis on the failure log file

After preparing the necessary input files, the next step is to write a script to run the scan diagnosis. There are four steps to run the scan diagnosis. First, the netlist and layout data are imported. Second, the test pattern file is loaded. The patterns loaded will be simulated and then verified by comparing the values before and after the simulation. This ensures that the test pattern and netlist match. Third, the expected value in a given failure cycle from the converted failure file is compared to the expected value in the corresponding loaded pattern. This ensures that the failure file and patterns match. Finally, the diagnosis will run on the failure log file, and a diagnosis report will be generated.

Industrial experiment result

The yield loss represented a 1% to 1.5% increase in stuck-at ATPG pattern failures. After the FA engineers spent six weeks trying to find the suspected defect location, scan diagnosis was introduced to the flow at the design site to support them, and the resulting suspect locations generated by diagnosis were provided to the FA engineers for physical failure analysis (PFA).Both logic-only and layout-aware diagnosis results were generated. The logic-only diagnosis report (Figure 4), revealed suspects with the highest score (100) as the perfect targets for PFA.

 

Figure 4: Logic-only diagnosis report

 

 

Although the suspected area can be found in the layout using the pin or net path name given in the report, doing so manually can be time-consuming because a net can cross a large area. Compared to the logic-only diagnosis flow, the layout-aware diagnosis flow is more efficient because the suspected area is directly reported as bounding box or enclosing circle (Figure 5). The layout-aware diagnosis flow was finally adopted because it was found to be significantly more convenient and efficient. 

Figure 5. Layout-aware diagnosis report

Overview of diagnosis results

Ten failure log files generated from the ATE were used to run scan diagnosis. The following rules were followed to guide the selection of diagnosis results to use for PFA: 

* Select the diagnosis result that contains suspects with a score of 100.

* Select the diagnosis result with the fewest number of symptoms and suspects.

As listed below in Table 1, 70% of the diagnosis results had suspects with scores of 100, which suggests that the failures on the tester completely match the failing behavior of the suspects. After applying the selecting rules, the diagnosis results from failure logs 3, 5, and 7 were chosen for PFA.

 

Table 1: 70% of the diagnosis results had suspects with scores of 100, which suggests that the failures on the tester completely match the failing behavior of the suspects. After applying the selecting rules, the diagnosis results from failure logs 3, 5, and 7 were chosen for PFA.

The FA engineer spent approximately one week to produce results, which matched perfectly with the diagnosis reports. A broken poly defect was found on all three die and was determined to be the root cause of the yield loss. Root cause of the yield loss was found to be caused by a variation in the manufacturing process. The layout-aware diagnosis methodology shortened the PFA cycle time from six weeks to two weeks.

One of the PFA results is illustrated in Figure 6. The FA engineer located the suspected area for PFA analysis based on the physical location reported in the bounding box (Figure 6), and the broken poly defect was found on one cell in the suspected area during the PFA phase.Figure 6: Physical failure analysis result.

Figure 6: Physical failure analysis result

 

Conclusion and next steps

We implemented a diagnosis flow for compression scan pattern failures. The experiment results demonstrated that the Tessent Diagnosis tool was able to precisely diagnose and report the suspected area, and the PFA result matched well with it. This flow shortened the FA cycle time from about six weeks to two weeks.In this case, we were able to identify a systematic defect from the PFA results. Often, if the yield loss is caused by a hidden systematic defect, it is very time-consuming and costly to identify it because the FA engineer must iterate through the diagnosis and PFA process until the hidden systematic defect has been identified. Future work is to set up a diagnosis-driven yield analysis approach [4] to address this challenge using Mentor Graphics Tessent YieldInsight tool. This analytic tool quantifies the systematic and hidden systematic defects based on the automatic analysis of multiple scan diagnosis reports and helps select the best candidates for PFA. The main advantage is a reduction in the FA engineer’s cycle time when the systematic defect can be identified before the PFA, and then PFA only needs to be used to verify the accuracy of the identified defect.

References

1. A. Leininger, P. Muhmenthaler, W.-T. Cheng, N. Tamarapalli, W. Yang, K.-H. Tsai, “Compression Mode Diagnosis Enables High Volume Monitoring Diagnosis Flow,” IEEE International Test Conference, Nov. 6–11, 2005, Paper: 7.3. 

2. Y.-J. Chang, et al., “Experiences with Layout-Aware Diagnosis,” Electronic Device Failure Analysis, May 2010.

3. A. Gattiker, P. Nigh, R, Aitken, “An Overview of Integrated Circuit Testing Methods,” Microelectronics Failure Analysis Desk Reference Manual, 6th edition, ASM International.

4. S. Palosh and G. Eide, “Scan diagnostic analysis assists SOC fab debug/process monitoring,” Solid State Technology, June 2011.

 

About the authors:

Thryambak Chandilya is an Applications Engineer at Mentor Graphics and has over 10 years of experience in Design-for-Test. He graduated from the University of Florida in 2000 with a Master of Science in Electrical and Computer Engineering.

Hu Sun is a DFT engineer in Freescale Semiconductor (China) Ltd.  His interests include Memory BIST and diagnosis-driven yield analysis. He received his Master’s degree in Information and Communication Engineering from Zhejiang University in June 2006 in Hangzhou, Zhejiang Province, China. He received his B.S. degree in Electronic and Information Engineering in June 2004 in Zhejiang University.

Wanggen (Andy) Zhang  is  DFT engineer in the Microcontroller Solutions Group of Freescale Semiconductor (China) Ltd, with more than 10 years experience in IC design and 7 years of experience in DFT. He graduated from  Zhejiang University with M.S. degree in 2000.

 

 
 

 

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