Partitioning an ASIC Design into Multiple FPGAs

by Juergen Jaeger, Synopsys Inc. , TechOnline India - August 04, 2010

Today's FPGAs are large enough to contain a complex system-level design. It's practical, however, for these designs to be partitioned among several FPGAs for various reasons. For example, you may invariably need external components in your system. Also, using several smaller devices can enable a more cost-effective solution than using one big FPGA. But, integrating your design into several FPGAs can create interesting partitioning problems, especially for larger and/or highly connected designs.

Most of today's system-on-chip (SoC) designs rely on field-programmable gate arrays (FPGAs) as a way to accelerate verification, start software development early and validate the whole system before committing to silicon. The FPGA may be an intermediate or, because tough economic realities cannot justify $1M+ in non-recurring engineering charges for an ASIC, initial implementation platform for the SoC design.

Today's FPGAs are large enough to contain a complex system-level design. It's practical, however, for these designs to be partitioned among several FPGAs for various reasons. For example, you may invariably need external components in your system. Also, using several smaller devices can enable a more cost-effective solution than using one big FPGA.

But, integrating your design into several FPGAs can create interesting partitioning problems, especially for larger and/or highly connected designs.

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