Successful Adoption of DFM

by Mark Redford, Cambridge Silicon Radio, and Jean-Marie Brunet, Mentor Graphics , TechOnline India - February 16, 2012

Two factors are now influencing the use of DFM for IC development at 28 nm and below. First, foundries now require or strongly recommend DFM checks for advanced nodes; second, some companies have discovered that DFM can be a source of competitive advantage.

By now, the challenges of production at advanced process geometries are well-known. Even though EDA companies and foundries have been developing and perfecting design for manufacturing (DFM) technology for many years now, in anticipation of their customers’ critical needs, many designers viewed DFM tools with skepticism as they continued to get products to market without them.

However, two factors are now influencing the use of DFM for IC development at 28 nm and below. First, foundries now require or strongly recommend DFM checks for advanced nodes, essentially equating them to traditional design rule checks. This requirement implies a shift in responsibility—customers not running DFM checks during design verification may find the foundry less willing to address yield issues when the product goes into volume production. Second, some companies have discovered that DFM can be a source of competitive advantage, and are aggressively deploying it to wring more performance out of and/or increase reliability of their designs at leading-edge process nodes.

Cambridge Silicon Radio (CSR), a leading supplier of wireless SoCs for the mobile communications industry, is one of those companies that recognize the competitive value of DFM, and are actively employing DFM tools and technologies to ensure high yield manufacturing of their high-performance analog/radio frequency (RF) system-on-chip (SOC), while also delivering performance and die size that gives them a market advantage.

The higher functionality required for CSR’s sophisticated designs demands higher digital gate counts and improved performance, driving the transition to advanced nodes. At the same time, with 40-50% of a typical CSR chip containing analog circuitry, analog/RF performance is crucial. Compounding the challenge, the mobile communications product market is highly fluid, meaning first-time working silicon and fast ramps to high yields are essential to profitability and market leadership.

To deploy the new functionality and design complexity needed, CSR has been transitioning to leading-edge process nodes while adding new product features and striving for optimum performance.  As part of this move, they added a variety of DFM techniques to their design flow. However, they recognized that simply trying to implement new nodes and design techniques without a plan would be disastrous, so they established objectives for their adoption of DFM for a core product:

• Design infrastructure in place and debugged ahead of the designers’ need
• Foundry technology aligned to CSR needs and requirements
• Hit schedule, functionality and performance targets for product development
• Develop robust intellectual property (IP) for re-use in application-specific standard products (ASSPs)
• Hit volume ramp on time without “manufacturing surprises”

By specifically outlining their objectives in advance, CSR was able to analyze each objective and determine the crucial elements for obtaining that objective. For example, they realized they would have to engage with pre-production processes to avoid creating layouts containing errors not discovered until later in the flow. They also began early engagement with the foundries, to ensure that they were aware of, and aligned to, the types of designs CSR would be sending to them. 

They also considered the implications of not adopting DFM technology. CSR knew from experience that working with a process in which not all effects are fully understood or characterized leads to unknown and/or unpredictable results. For example, in the pre-silicon phase, GDS supplied to the foundry can fail due to optical proximity correction (OPC) errors, or the fill may not satisfy requirements, necessitating a return to CSR for correction, increasing design cycles and negatively impacting time to market. Post-silicon, there is the chance that the part will fail in testing, requiring lengthy and complicated debugging and failure analysis, drawing out the time to market even more. By implementing a well-thought-out design philosophy that incorporated DFM within the CSR layout guidelines, design reviews, and tapeout procedures, they hoped to reduce these unknowns by predicting and understanding the process effects earlier in their design flow. In the end, they wanted to have high confidence that the designs they sent to the foundry would pass internal checks, and reduce debugging and failure analysis time and complexity, thereby improving time to market and competitive advantage.

To deploy DFM most effectively, they first formed a cross-functional team consisting of process technologists, designers, layout engineers, and electronic design automation (EDA) specialists. They evaluated DFM technology not just for its capabilities, but also for the supplier’s relationship with the foundries. Having a strong collaboration between CSR, the EDA supplier, and the foundry was essential to facilitate the process of understanding, capturing, and mitigating the underlying effects of the process.

Next, they established a deployment plan and identified joint projects needed to address specific CSR product requirements and ensure they were addressing both systematic and random effects. Four projects were instigated:

• Critical Area Analysis (CAA) to perform analysis on all standard cells and adjust the cells with the greatest sensitivity
• Litho-Friendly Design (LFD) analysis to perform lithography simulation on analog/RF IP and digital cells and adjust layout styles found to be susceptible to lithography effects
• Chemical-Mechanical Polishing (CMP) analysis to perform CMP simulation and identify thickness variation concerns across the die

Fill analysis to analyze the impact of different fill options on transistor and design behaviorRunning CAA through digital blocks revealed that the use of single vias had a big impact on yield, given the defect density values of the manufacturing process. Optimizing via redundancy resulted in a significant improvement (Figure 1). Using this data, CSR were able to modify their place and route (P&R) setups to minimize the use of single vias.

 


 
Figure 1. Via redundancy optimization provided a significant improvement in yield.

Using LFD analysis allowed CSR to optimize its layout style to avoid potential lithography issues such as gate corner rounding. As shown in Figure 2, the OD contour variation can cause width deltas and the poly contour can cause length deltas that result in unacceptable gate rounding. With LFD analysis identifying these potential issues early in the design flow, the layout guidelines can be improved to adjust poly to OD spacings, and avoid these effects for sensitive analog circuitry.

 

Figure 2. LFD analysis allowed CSR to identify lithography “hotspots” during the design process.

CSR used the CMP analysis in conjunction with the “smart” filling techniques of the DFM tool to analyze the thickness and density before and after fill is applied, and achieve a tighter fill distribution (Figure 3). Using these two DFM techniques in tandem enabled CSR to ensure that density and planarity issues were addressed using the appropriate parameters to reflect silicon behavior.

 


 
Figure 3. Using sophisticated fill algorithms in combination with CMP analysis, CSR was able to obtain a tighter fill distribution and a flatter design.

 

By engaging wholeheartedly in the DFM implementation, CSR was able to define and apply the critical success factors of the DFM process—first, to understand the impact of the effects addressed by DFM technology and implement design guidelines to minimize their occurrence through careful design, and second, to quickly and efficiently identify and fix any occurrences once the design is underway.

The internal results of CSR’s targeted DFM implementation were as follows:

• Optimization of specific aspects of the CSR design flow
• Optimization of some CSR design styles
• Identification of third-party IP weaknesses

In turn, these results had a direct impact on product success. Not only did they achieve yield earlier than planned, but the product performance exceeded expectations. CSR’s proactive approach to DFM implementation substantially reduced their manufacturing risk while improving their competitive position in the market. In addition, their improved design flow and layout style optimizations not only allowed them to achieve their specific target in this project, but increased their chances of success with future designs as well. The successful implementation and application of all of these DFM tools and techniques were not one-time events, but the result of ongoing collaboration and continual process and design adjustments to incorporate lessons learned.

About the Authors:

Mark Redford: With over 25 years in the semiconductor industry, Redford’s career spans engineering leadership positions at IDM, foundry, consultancy and fabless companies. He is currently the general manager of North American Operations & vice-president of Advanced Process Technology Development at CSR, a leading wireless IC maker. Redford earned a B.S. in Electronics and PhD in Semiconductor Engineering from the Universities of Dundee and Edinburgh, Scotland, respectively.

Jean-Marie Brunet: Jean-Marie Brunet is the director of product marketing for Model-Based DFM and Place-and-Route Integration at Mentor Graphics Corporation. Over the past 15 years, he has served in application engineering, marketing, and management roles in the EDA industry, and has held IC design and design management positions at STMicrolectronics, Cadence, and Micron, among others. His experience includes working with pure-play foundries to resolve complex yield issues related to OPC and RET. He holds a Master's degree in Electrical Engineering from I.S.E.N. Electronic Engineering School in Lille, France.

Article Courtesy: EDA DesignLine

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