Picking the right built-in self-test strategy for your embedded ASIC

by Sunit Bansal and Sumeet Aggarwal , TechOnline India - August 11, 2010

Test time is a significant component of ASIC cost. It needs to be minimized and yet has to have maximum coverage to ensure zero-defect scenario for an automotive application. Such test modes usually accompany memory built-in self test (MBIST) mode, which goes through all the bit-cells for all memory banks in a design.

Test time is a significant component of ASIC cost. It needs to be minimized and yet has to have maximum coverage to ensure zero-defect scenario for an automotive application. Such test modes usually accompany memory built-in self test (MBIST) mode, which goes through all the bit-cells for all memory banks in a design.

Depending on the implementation of BIST module (Figure 1, below), we may have parallel and serial access capabilities to test the same. This test is performed at wafer level and package level. We usually have multiple packages available for SoC, which has a different number of power pads available.

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