System awareness improves SOC power management

by Satish Sathe, Senior Systems Architect, Applied Micro Circuits Corp. , TechOnline India - March 31, 2011

Reducing the power consumption of SOCs (system on chip) has become increasingly important in electronic system designs, even when there are no batteries involved. Improvements in device-level methods are one step in the enhancement of SOC power management. Adding system and application awareness, however, can amplify the effectiveness of those efforts significantly.

Reducing the power consumption of SOCs (system on chip) has become increasingly important in electronic system designs, even when there are no batteries involved. Improvements in device-level methods are one step in the enhancement of SOC power management. Adding system and application awareness, however, can amplify the effectiveness of those efforts significantly.

The benefits of power management in battery-operated systems are obvious. The lower the average power consumption, the smaller, lighter, or cheaper the battery can be. When using stock commercial batteries, lower power means longer operating life. Either way, lower power translates to greater customer satisfaction.
Increasingly, however, power management is becoming critical in line-powered systems as well. Managing system power consumption yields multiple benefits. In data centers, for instance, the server farms are seldom fully loaded, yet never completely off. As a result, they can consume nearly half their total power simply idling.

Most consumer electronics systems also dissipate power when nominally “off” because they must remain active enough to respond to remote controls, and similar functions. Such “vampire” systems are estimated to account for nearly 10% of household energy use in the US, wasting some $3 billion worth of energy. System power management can reduce such waste considerably. Power management can also remove performance constraints on system designs, especially in systems such as Power over Ethernet (PoE) that have limited power available.

Even with unlimited power availability, though, managed power can eliminate constraints by reducing a system’s need for heat sinks and other cooling mechanisms. This helps the design avoid compromising performance in order to meet physical constraints such as limits on heat-sink size or on air flow. A reduction in the cost of system cooling is an additional benefit.

Increasing government regulatory actions also foster the need for power management. The Federal Energy Management Program in the US, Europe’s International Energy Agency, and Australia’s Department of Climate Change are all demanding that electronic systems constrain their power consumption, especially in modes where the systems are not doing useful work.

SOC key to system power management

In modern electronics, system power management essentially means working with the heart of the system: the SOC device, which provides or controls every major system element. Opportunities for power savings within an SOC are greatest at the system level, which deals with functional blocks within the SOC as single elements (Figure 1).

 

                                   

Figure 1: Power-management schemes which slow or shut down functions that are not in use can maximize power savings, if they can treat functional blocks as single entities.

For instance, in many designs there are functional blocks that applications call upon only rarely. These blocks may be essentially shut down when not needed and become active only on demand. Such behavior would have little impact on the device’s performance as seen by the user, but can yield significant power savings.

The frequently-used blocks in an SOC are typically not all fully loaded for any given task, so may not need to operate at their full performance capacity at all times. System-level SOC power management can trade a block’s performance for reduced power demand to take advantage of such load variations. As with shutting down seldom-used blocks, this performance reduction is imperceptible to the end user but results in considerable power savings.

System-level power management within an SOC can also take advantage of low-power modes on interfaces such as Ethernet, PCIExpress, and USB. When no data is flowing, power management can set the interface to a low-power mode without sacrificing connectivity. Further, the SOC as a whole can implement a variety of standby modes with different combinations of functional blocks in low-power states to optimize system wake-up response times against power draw. Such modes in the SOC give even more even flexibility to power management at the full system level, where the SOC’s behavior can be coordinated with other system elements such as disk drives, displays, and cooling fans.

The effectiveness of system-level power management increases when the management scheme is aware of what the system is trying to accomplish (Figure 2). Running an e-mail program is less performance-intensive than playing music, so it can run at a lower CPU clock rate. Music, in turn, needs less performance (and power) than streaming video.

                                     

 Figure 2: Being aware of what application a system is running allows power management to control power and performance tradeoffs for system blocks more effectively than simple inactivity timeouts.

A power management scheme that can detect in which activities the user is engaged can more efficiently control power usage by individual system elements than a scheme which depends on vague clues such as activity timers. Such application awareness also avoids user-annoying, inadvertent shutdowns of needed system elements, such as dimming a monitor during video playback just because no keyboard or mouse activity has been occurring.

Power management can also increase its effectiveness by being aware of timing patterns in system usage. A system server in an enterprise setting, for instance, can save power by not jumping to its peak performance when user activity is detected after hours or on weekends. During such low-load periods the system does not need to support many simultaneous users, so even at a reduced performance (i.e., low power) setting a solitary user will not notice a decrease in system response.

Performance monitoring essential to power management

An effective SOC power management scheme, then, has several attributes. For one, it must be able to measure, profile, and report on functional block usage so that it (or the user) can determine the optimum power and performance settings of various functional blocks during key applications. It should be able to control functional blocks both within the SOC and in the outside system to provide coordinated power settings. It should also not intrude into the user’s experience and operate transparently to the application and operating system software.

To achieve these goals, the power management scheme will require a combination of hardware and software elements in a customizable implementation integrated into the SOC. The software basis will allow customization of the management scheme to suit specific needs and ideally will utilize a standard instruction set architecture to ease customization. The hardware basis will help offload tasks from the CPU so that power management can continue operating even if the processor is shut down to conserve power.

One such power management scheme is embedded in AppliedMicro PacketPro multicore SOC family devices. The scheme dedicates one of the SOC’s processor cores - designated the SLIMpro (scalable lightweight intelligent management processor) – to handle power management for the entire PacketPro device (Figure 3). The SLIMpro’s operation serves as an example of the many power-saving opportunities available in an SOC design.

                                  

Figure 3: An integrated power management processor scheme, such as SLIMpro, can control SOC functional blocks, manage queues and traffic, and monitor and control off-chip system functions such as fans.

 

Power management in the SLIMpro begins at the control level, using an industry-standard Intelligent Platform Management Interface (IPMI) for access to, and control of, the power management activity. The IPMI interface is active when the SOC is in operational or standby states and, because it runs on the dedicated processor, is independent of the applications processors and OS.

This interface allows the power management processor to provide remote system management, obtaining status information, reviewing logs, and issuing requests to other system elements without using the application processors. The power management processor can also monitor system temperature sensors and control system elements such as fans and power supplies, independently of the SOC’s current state.

Sideband connections enhance standby modes

The power management processor also utilizes sideband connections to the SOC’s high-speed I/O ports. The connections are shared in an OS-independent fashion between the power management processor and the main processors when they are in an active state, which provides a sideband network interface for the IPMI. When the rest of the SOC is in sleep mode, this connection allows power management to take over these interfaces and decide when I/O activity is allowed to wake the SOC.

For instance, if the SOC is part of a server, the power management can save power by refraining from waking the SOC for every message coming across the LAN. The side loading allows power management to monitor the LAN connection and see whether or not the incoming traffic is destined for the SOC. If traffic targets the SOC, power management can buffer the incoming message to avoid losing packets while waking the SOC to handle the message. If the packet is not destined for the SOC, power management allows the SOC to remain asleep.

Additionally, the power management processor can respond to simple actions such as network pings and remote status queries without waking the SOC, thus minimizing the need for the SOC to transition to active state. Other ports, including USB, PCIe, timers, and interrupts can likewise be intercepted by the power management processor to buffer data while the SOC wakes.

The power management processor controls the power and performance of the SOC’s functional blocks when active through a combination of clock gating and frequency scaling. When a block is not currently needed, turning off its clock saves power without altering its state. If a block is needed, frequency scaling allows it to operate at reduced power while operating at a sufficient, but below maximum, performance level. For memory, the power management processor can invoke the DDR self-refresh mode to save power in the memory interface while access is not needed.

One way the power management processor handles frequency scaling for offload engines (such as compression and encryption) in the SOC is to use a QMTM (queue management traffic management) block that controls traffic flow and monitors the status of the queues between the engines. When a queue in one element of a chain is full, there is no need for the preceding element to operate at its full clock speed and simply burn power while the element waits for its output queue to accept new data.

Thus, power management can, where appropriate, lower the element’s clock speed until the queue opens, providing a dynamic frequency scaling of offload engines to maintain maximum throughput while minimizing power. This activity can be implemented in hardware for fastest response time and to eliminate software overhead.

Deep sleep maximizes power savings

All these control and connectivity capabilities of the power management processor allow the implementation of a “deep sleep” mode for the SOC. Designing the SOC to have several different power planes allows power management to turn off system elements completely, and eliminate their power demand during deep sleep. The power management processor stores the system state so that the SOC can awake quickly and fully configured, preserving security associations, link characteristics, and similar.

During such deep sleep, the only SOC elements that remain powered are the memory subsystem, the I/O interfaces, and the power management processor. The memory controller is powered on, but is clock-gated to remain static while the subsystem utilizes the DDR memory’s self-refresh mode. This allows the memory subsystem to minimize power, yet quickly exit deep sleep in the event of a wake-up event to begin buffing I/O data while the rest of the SOC is re-initializing.

Similarly, the I/O interfaces can be in a low-power state, and the power management controller can be in standby, waiting to wake on I/O activity or in response to a timer. In the PacketPro SOC, such a deep sleep state brings the device’s total power draw down to under 200mW.

Such ultra-low power sleep modes will be increasingly important in SOC designs. An International Energy Agency is calling for all new electronic system designs to require less than 1W total system power when in standby mode. In the US, government mandates require all new electronics systems purchased under Federal programs comply with this 1W Initiative.

Integrated system power management in SOC devices will be essential to meeting these goals. By having the intelligence to monitor and respond to usage statistics as well as by being application aware, SOC power management can optimize the power and performance of system blocks to dynamically match application requirements. Implementations, such as AppliedMicro’s SLIMpro, for example, show just how effective such power management can be.


About the author:

Satish Sathe is a senior systems architect at Applied Micro Circuits Corp., (recently AppliedMicro, Inc.) where he is responsible for SOC-architecture and -feature definition. He has more than 20 years of experience in building and designing state-of-the-art network-switching systems and controllers and has played key architecture roles at LSI, Stratacom (acquired by Cisco Systems), Acclaim Communications (acquired by Level One and then acquired by Intel), Ample Communications, and Brocade. Sathe holds a Master’s Degree in electrical engineering from the University of Illinois—Urbana-Champaign.
 



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