The next transistor: planar, fins, and SoI at 22nm

by Ron Wilson , TechOnline India - July 20, 2011

Process developers working on 22/20nm logic processes are scrambling to introduce new transistors for this node. This is fascinating for device designers, but not for chip designers. But decisions on transistor design will have profound impacts — from the craft of cell design to the work of physical design teams.

The race is on to redefine the transistor. Process developers working on 22/20nm logic processes appear to be scrambling to introduce new kinds of transistors for this node. Intel has made a huge fanfare over their tri-gate device. Many researchers are pushing finFETs. A powerful group of mainly European organizations, including ARM and US-based Globalfoundries, is serious about fully-depleted SoI (fdSoI.) And recently, start-up Suvolta and Fujitsu described yet another alternative.

All this might appear fascinating for device designers, and irrelevant to chip designers. But decisions on transistor design will have profound downstream impacts—from the craft of cell design to the work of physical-design teams, and even to the logic designer’s struggles with power and timing closure.

 

What’s the problem?

Why are process engineers so determined to upset the apple cart? The short answer is short-channel effects. Pursuit of Moore’s Law has continually shrunk the channel length of the MOSFET. This contraction improves transistor density and, other factor fixed, switching speed. The problem is that shortening the channel plays havoc with those other factors—about a dozen different havocs, actually, that get lumped under the label of short-channel effect. Most of these we can summarize by a generalization: as the drain gets closer to the source, it gets harder and harder for the gate to pinch off the channel current (Figure 1). The
result is sub-threshold leakage current.

                             

 

 Figure 1. Short-channel effect eats away at the gate's control over the channel

 

 

This battle against leakage current has been going on since at least the 90 nm node. The point of the whole high-k/metal-gate (HKMG) transition was to give the gate more control over the channel current without letting gate leakage get out of control. But by the 22 nm node, many are arguing, the planar MOSFET will have lost that war. There will be no way to deliver adequate leakage control at adequate performance. “With HKMG we addressed gate leakage,” one expert said. “Now we have to address channel leakage.”

Planar one more time?

Not everyone agrees that the planar MOSFET is history. Principal among the dissenters is TSMC, which stated in February that it would use planar transistors in its 20 nm foundry process. There are strong arguments for this position, also held—with one major caveat — by Globalfoundries. Designers are familiar with short-channel planar MSOFETs, for all their shortcomings. This should make rescaling of cell libraries and hard IP blocks relatively straightforward. Leakage and threshold variations may be worse than at 28 nm, but the design community has tools, including aggressive power management, variation-tolerant circuits, and statistical timing analysis, to cope with these problems. And when all the issues are on the table, a foundry must do what its lead customers—FPGA vendors, networking IC giants, and to some extent ARM—ask of it.

Still, there is much skepticism. “TSMC stated that they would use a replacement-metal-gate planar process at 20 nm,” observed Novellus vice president Girish Dixit, “but that determination may have changed. HKMG can control leakage, but a planar transistor will still have inferior I-on/I-off characteristics.” If TSMC’s early adopters find themselves at a competitive disadvantage because of the planar transistor, they may force the giant into a finFET half-node. The confrontation would most likely arise in the mobile market, where ARM’s fabless silicon partners will face competition from Intel’s Atom processor, newly rejuvenated by that company’s 22 nm tri-gate process.

The rise of the fin The next-transistor debate matriculated from a decade in the
cloistered but technically accurate halls of process engineering conferences to the public forum with Intel’s May announcement of their 22 nm so-called tri-gate process. The roll-out, probably intended to counter ARM’s growing momentum in the mobile space rather than to advance the discussion in circuit design, significantly reduced the signal-to-noise level about new transistor technology.

Intel’s tri-gate device is a finFET, pure and simple. Industry experts dismiss Intel’s attempts to claim a significant difference. As such, it is one instance of a decade-old, industry-wide attack on short-channel effect—an effort that began at industry consortium IMEC at about the same time as it did at Intel. “Everyone in the industry has been developing finFET technology,” one process expert said. “The difference is in what they have chosen to announce.”

All finFET programs—indeed, all the approaches to next-transistors — rest on a single concept: the fully-depleted channel. Loosely, the concept is to give the gate so much control over the electric field in the channel that the gate can deplete the channel of carriers entirely. This of course eliminates the dominant conduction mechanism in the channel, and in effect turns the transistor off.

But how to do that? In a planar device, the depth of the channel and effects from the junction formed between the drain and the silicon around it alter the electric field in the channel and interfere with depletion. Somehow you have to make the channel thin enough and far enough from the drain junction to permit the gate to fully deplete the conduction region.

The finFET solution is to stand the channel on its edge, above your choice of either the silicon surface or an insulating oxide layer, and to drape the HKMG gate stack over the resulting fin like a wet blanket. This fin-shaped channel is very thin (Figure 2) and working from three sides, the gate can successfully create a depletion region that blocks the channel entirely. 

 

             

 

 

The finFET gives circuit designers a V-I curve they’ve only been able to dream about since 130 nm. But it also brings issues. One is simply building the devices. “Making the fins, and preserving them through subsequent processing steps, are hard tasks,” warned Applied Materials Silicon Systems Group vice president and CTO Klaus Schuegraf.

“You must etch over the edges of tall structures, uniformly dope complex 3D
surfaces, and lay down all the different films in the gate stack so that they conform exactly to the surface of the fin. These requirements bring about many changes in materials, and some changes in equipment. The number of mask layers won’t change much, but the number of processing steps will certainly go up.”

 

Fins and the rest of us

There will be issues for chip designers as well. The fin width will be the minimum process dimension. In order to form the fins, a double-patterning lithography technique—probably spacer-defined — will be mandatory. Double-patterning, in turn, will impose “very restrictive design rules,” Schuegraf said. Intel director of components research Mike Mayberry added clarification: “Most of the design rules are litho-dominated. Once you can make features at 22 nm, there are few
rules that are specific to the tri-gate structure.”

FinFETs will bring changes for circuit designers, too. The most obvious one is that you can’t change the width or height of a fin to increase drive current. “One fin is one quantum of drive current,” Mayberry said. The height of the fin is determined by a polishing step, and so is constant—as much as possible—across the wafer. But the width of the fin isn’t flexible either.

This limitation, according to Dixit, is not simply due to lithography restrictions, but is mainly due to the fact that if you widen the fin, the threshold voltage starts to roll off. If you widen the fin to get more drive, you accidentally change the threshold voltage as well.

Incidentally, this also means that any variation in line width at minimum geometry, just like any variation in polish depth during fin formation, translates into threshold variation at the transistor level.

To get higher current, you put more fins in parallel. Of course only being able to change drive current by fixed increments will be a new limitation for circuit designers, especially in the custom analog world.

But Intel is not worried. “We’ve modeled tri-gate circuits extensively in both switch and amplifier applications, and we believe very few circuit designs will require modifications,” Mayberry said. Others are less sanguine. “For high current you have to parallel the fins,” said IMEC executive vice president of business development Ludo Deferm. ”But that requires interconnect between the transistors, and at high frequencies the interconnect resistance becomes a factor in circuit performance.”


Another route to full depletion

The supporters of fully-depleted silicon –on-insulator (fdSoI) argue that they can offer the V-I characteristics of finFETs without the problems. The fdSoI transistor is a simple planar MOSFET fabricated in the ultra-thin layer of undoped silicon atop the buried oxide layer of an fdSoI wafer. There are many advantages to the device; mostly, it is a conventional MSOFET with width scaling, no memory effect, and, according to Leti laboratory leader Olivier Faynot, your choice of either 60 percent more speed or 50 percent lower power at circuit level compared to competitive processes.

Perhaps more significant is threshold voltage control. Because the fdSoI channel is undoped, there is no problem with variations in channel doping causing threshold variations—an issue that plagues both planar and fin devices as fewer and fewer dopant atoms go into the channel.

Further, there is the issue of providing multiple threshold voltages in the process. Planar and fin FETs must change threshold voltage by changing doping level: a process complexity for planar, and probably completely infeasible for fins. But fdSoI, Faynot said, can control threshold voltage dynamically by applying a back-bias voltage to the underside of the channel through the ultra-thin buried oxide.

Standing against all these advantages are three relatively non-technical issues. First, fdSoI wafers are more expensive than conventional wafers. But last week wafer vendor Soitec distributed a report from analyst IC Knowledge claiming that because of the significantly simpler processing to provide multiple threshold voltages on fdSoI wafers, the total cost of a processed wafer at 22/20 nm would be no greater for fdSoI than for planar or finFET processes.

Second, there is risk. Soitec is the only source of wafers for fdSoI, and creating the wafers requires executing the company’s oxide-deposition, wafer-splitting, and polishing steps with atomic-level precision. Soitec delivers the wafers with a uniform 12 nm film of  silicon over a similarly thin buried oxide layer. Third, there is inertia. Many senior decision-makers won’t consider anything that’s called SoI.

Still some companies will press ahead. AMD, through its Globalfoundries connection, IBM, and ST are probably committed to fdSoI at 22nm. In fact Globalfoundries, which in the past has not aggressively marketed SoI to customers not already using the process, may use fdSoI as an ace up the sleeve to counter pressure from Intel and to trump TSMC. Some fabless IC vendors who have used partially-depleted SoI already, such as Broadcom, are likely to listen to this argument. Beyond this core, though, “fdSoI may just not get the attention,” one insider worried.

There is one more announced player in this race. SuVolta recently announced a process in which the start-up uses deposition to create a buried junction under the channel of a conventional bulk planar MOSFET.

Reverse-biasing this junction creates a depletion region under the channel that in effect mimics the buried oxide layer of fdSoI, thinning the active region of the channel until the gate can almost fully deplete it.

The SuVolta technology is interesting, but not widely known outside of a few non-disclosure partners of the start-up company. Consequently, there has not been independent verification of the characteristics of  the SuVolta mostly-depleted transistor. None the less, this may be an important alternative for smaller fabs — not unlike Fujitsu — that haven’t the funding to enter the finFET race, and don’t want to pay the extra initial cost for fdSoI wafers.

So there are the players. TSMC seems committed to supply a planar 20 nm
process, at least to its initial customers. But it may do a quick revision, and offer a finFET option for mobile applications well before it releases a 16 nm process. Intel is clearly committed to its finFET.

IBM, and parts of the Globalfoundries and ST capacity at 22 nm will likely be using fdSoI. Fujitsu will probably continue to exploit their joint development with SuVolta. How the other players line up will undoubtedly depend on customer demands and on early process learning from the major players. If 28 nm proved anything, the lesson was that the course of new process technology doesn’t often run smooth.

 

 

 

 

 

 

 

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