Programmability in portable design: the five modes of motivation

by Wendy Lockhart , TechOnline India - June 03, 2009

Wendy Lockhart explains that flash based FPGAs can replace ASICs in portable devices.

The last decade has seen rapid and permanent change in technology markets toward smaller, more portable systems; many large systems that once sat on a desktop are now portable, while portable devices that used to fit in a backpack or briefcase must now fit in a shirt pocket. This has brought many additional design demands, most obviously battery life. Time between recharging, once measured in hours, must now stretch for days.

Size and power considerations are now often the top priority in many system designs, but portability and long-lasting power can become conflicting design requirements. Design teams are continually challenged with packing more and more functionality into smaller and smaller packages, and then somehow squeezing enough power into the same package to keep everything running for days, weeks, or even months at a time on a single battery charge.

Meeting size and power requirements in portable devices typically requires application specific integrated circuits (ASICs). Increased market pressures comprising shortened development cycles and lower cost, however, make the time and expense required for ASIC development a high design risk. Taking time to design and debug an ASIC could lead to missing ever shrinking market windows, or drive development costs so high it's impossible to make a profit.

So what does a design team do? Field programmable gate arrays (FPGAs) are the answer. In many applications, FPGA functionality rivals and often surpasses that of an ASIC. But beware: not all FPGAs are created equal, especially in portable, low-power applications.

While a detailed description of an FPGA is beyond the scope of this article, a simple explanation will serve our purposes. If you opened the cover of an FPGA, you would find multiple programmable logic blocks and a network of customizable interconnects. Design teams program the device by connecting logic blocks, via transistors in the interconnections, to create custom functions. In an ASIC, the function performed by the transistors is achieved using fixed, metal interconnections, defined at the time of fabrication or 'spin'.

FPGAs offer design teams two key benefits: design flexibility and fast time-to-market. Using FPGAs, designers can create and test multiple design options in the time required for a single spin of an ASIC design. The result is a better design in a shorter time.

With these important benefits, you might wonder why FPGAs aren't used in more designs. The answer lies in process technology. FPGAs have traditionally been fabricated using static random access memory (SRAM) technology which results in a device with a large circuit board footprint and high power draw. These drawbacks limit an FPGA's utility in portable applications. FPGAs based on flash technology overcome these drawbacks and make programmable logic an ideal solution for portable devices.{pagebreak}

Actel Corp.'s industry leading low-power flash FPGA technology overcomes the size and power limitations of SRAM FPGAs. Actel's non-volatile, reprogrammable flash FPGAs use a single flash cell to form efficient interconnects. Compare this with the six-transistor cell interconnect used in SRAM FPGAs, which accounts for the larger footprint and higher power requirements. Actel's nano FPGA devices are available in packages as small as 3x3mm with power consumption as low as 2W.

Designing with FPGAs, however, is not without its challenges, particularly when developing low-power applications. Designers must look beyond device datasheets and consider the FPGA's entire power profile. An FPGA's power profile depends on five distinct modes of operation: Power-up mode, configuration mode, stand-by mode, active mode, and sleep mode. To determine total power requirements, design teams must calculate how much time the system spends in each mode of operation. Operating temperature must also be considered as FPGA power consumption varies directly with temperature.

Power-up mode: SRAM FPGAs are usually not configured at start up, a state they remain in until the initial power-up and reset sequence is complete. The power-up process includes ramping power supplies to their final value, ramping the system to a stable state, and configuring the FPGA based on system configuration information (see configuration mode below). The power-up sequence can create a current spike of several amperes lasting several hundred microseconds. To moderate the SRAM power-up surge, design teams often use complex power sequencing techniques, which add more cost and complexity to the system.

With restricted power sequences, standard voltage regulators cannot be used and more expensive power sequencing devices are required. Also since sequences may be different from the standard system voltages, the use of power planes may be limited as well, adding additional board layers. Actel's flash FPGAs feature a very limited power-on current surge and no high-current transition period.

Configuration mode: Once the power-up and reset sequence for an SRAM based FPGA is complete, the configuration sequence starts. In configuration mode, the FPGA is configured by a bitstream, downloaded from an external device. The configuration sequence can easily consume several hundred milliamps for several hundred milliseconds. This sequence repeats itself every time system power is cycled. Such power requirements may be acceptable for systems connected to the electric utility grid, but they are often unacceptable for portable, battery-operated systems, especially those with limited access to recharging. In contrast, Actel's flash FPGAs retain their programming, even if power is completely removed from the device. The result is no configuration cycle power-drain.{pagebreak}Standby mode: An FPGA may spend most of its time in standby mode, where the device is powered-up but not active. Power in this mode is commonly called static power. FPGAs are commonly used as co-processing devices, where parallel processing is required for data processing or image manipulation. In systems where the device may be waiting for user input, a simple processor can perform basic user interfaces, while waiting for an interrupt to indicate that it is time for the FPGA to power up and perform processing.

Even in this mode, SRAM FPGAs use significantly more power than flash FPGAs. Temperature also plays an important role in standby mode. At room temperature, SRAM FPGAs can draw 1000x or more static power than flash FPGAs, increasing at elevated temperatures. Even for portable devices that operate mostly in standby mode, flash FPGAs are the clear choice.

Active mode: In active mode, FPGAs perform operations based on their programming. The I/Os and logic cells are switching, and power consumption (of dynamic power) is a function of capacitance, operating voltage and switching frequency. If dynamic power were the only power component incurred through executing logic operations, power profiles for all advanced FPGA technologies would be similar. But the total power in active mode includes the dynamic power plus the static power. Even in active mode, SRAM FPGAs consume more power than flash-based devices, because of the significantly higher static power component. And as with stand-by mode, the power difference in active mode at high temperatures is even more pronounced.

Sleep mode: To conserve power in portable devices, particularly when idle, design teams commonly implement system sleep modes. Note that sleep mode is different from standby mode. In standby mode the device is powered-up but is not executing instructions; in sleep mode the device maintains only minimum power levels to ensure quick startup once the system is switched on. Without special design considerations (such as additional circuitry to compensate for sleep mode) SRAM FPGAs lose their configuration data and must be reconfigured before switching to standby or active mode; making this switch consumes configuration power.

Actel's flash FPGAs offer low-power modes via their Flash*Freeze technology. With simple single-pin Flash*Freeze activation, Actel's IGLOO nano FPGAs consume as little as 2W of power in sleep mode. Most SRAM FPGAs do not offer comparable modes, however one example does reduce static power from 350mW down to 200mW in suspend mode.

Power versus package size

In the portable marketplace, low-power technology is of little use without small scale packaging. Device footprint and thickness are important, as is the number of I/Os. Actel offers device footprints as small as 3x3mm with thicknesses down to a very thin 0.7mm, the smallest form factors in the industry. And by using micro chip scale technology with 0.4mm pitch packaging, Actel leads the programmable logic market in per device small scale package I/O.

Fast moving technology markets are forcing designers to replace ASICs with flexible FPGA technology to reduce design time and risk. Choosing the right FPGA technology is critical to design success in the portable, low-power market. SRAM FPGA's large device footprint and high power requirements make them unsuitable for these applications.

Actel's nano FPGAs enable programmable logic use in this fast moving market with device footprints as small as 3x3mm and power up to 1000 times lower than SRAM FPGAs in active, static and sleep modes. Finally designers have a realistic programmable alternative to ASIC technology.

Wendy Lockhart is principal engineer with Actel Corp.

This story appeared in the Janjuary-February 2009 print edition of Embedded Systems Europe

European residents who wish to receive regular copies of Embedded Systems Europe, subscribe here.

You can download a digital edition of this Embedded Systems Europe print edition here.

About Author

Comments

blog comments powered by Disqus