Synopsys mulls spinoff for design kit initiative

TechOnline India - November 08, 2009

Seeking to gain more support for its process design kit (PDK) initiative, Synopsys Inc. demonstrated its PDK technology and disclosed the idea of possibly spinning out the effort.

SAN JOSE, Calif. -- Seeking to gain more support for its process design kit (PDK) initiative, Synopsys Inc. demonstrated its PDK technology and disclosed the idea of possibly spinning out the effort.

The EDA giant provided a working demonstration of a PDK, based on the technology from the Interoperable PDK Libraries (IPL) Alliance. The IPL is attempting to devise a standard PDK for analog/mixed-signal designs. Much of the IPL work--and associated resources--are being driven and conducted by Synopsys (Mountain View, Calif.).

To garner more support for the technology, Synopsys is mulling plans to spinoff or ''spawn'' the IPL initiative effort into a ''standards organization,'' said Ed Lechner, director of product marketing for custom design at Synopsys, at the EDA Interoperability Forum last week.

Lechner did not elaborate, saying no decision has been made about the future of the IPL initiative. That's just one possible option for the IPL group, an initiative that includes Magma, Mentor, Synopsys, TSMC and other tool and intellectual-property (IP) vendors.

Today's analog-oriented PDKs are proprietary and incompatible. And TSMC and others are forced to support separate and proprietary custom-oriented PDKs from Cadence, Mentor, Synopsys and others.

The PDK from the IPL is supposed to reduce cycle times and costs. Recently, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has made good on its promise from last year, in which the foundry vendor and IPL talked about delivering a PDK for 65-nm designs. The new so-called iPDK from TSMC supports a full custom design flow from schematic entry to final layout verification.

Tom Quan, deputy director of design services marketing at TSMC (Hsinchu), said the foundry giant's ''customers are starting to use'' the IPL-backed PDK based on 65-nm technology. The silicon foundry giant, Synopsys and others are also devising analog/mixed-signal PDKs for TSMC's 40- and 28-nm processes, Quan said at the EDA Interoperability Forum.

The big question is clear: When will other foundries and integrated device manufacturers (IDMs) jump on the IPL bandwagon? To date, TSMC is the only foundry to endorse IPL. No other foundries and IDMs have publically endorsed it.

In fact, there are some misconceptions that IPL is a TSMC-run organization. This, of course, is not true, but TSMC's efforts in IPL are making others weary about the group.

One analog foundry, which uses Cadence Design Systems Inc.'s rival custom EDA tools, is eyeing the IPL technology. ''We're looking at (IPL)," said Lou Hutter, senior vice president and general manager of the Analog Foundry Business Division at South Korea's Dongbu HiTek (Seoul). Hutter said Dongbu has not made a commitment to use the IPL technology.

Most--if not all--chip makers use Cadence's custom EDA tools for analog and mixed-signal. Cadence's custom tools have been around for years. The IPL is attempting to unseat Cadence's monopoly in the arena.

Cadence's tools are said to be interoperable with the IPL initiative. But Cadence has also not joined IPL, creating some challenges for the IPL to sell its technology.

''Change is difficult'' in the analog/mixed-signal world, said Lechner. So for now, it's hard to call the current PDK technology from IPL a standard. Going forward, the goal is to gain more support from other foundries, fabless firms and IDMs, he said.

During the EDA Interoperability Forum, Synopsys outlined the future directions of IPL technology in order to make it more of a standard and garner more support. Here's the plan:

1. Evolve the IPL Alliance into a standards body. The idea is to ''spawn'' IPL into a standards organization, but no decision has been made. One idea is to spinout the initiative into the Silicon Integration Initiative (Si2), an organization of industry-leading companies in the semiconductor, electronic systems and EDA tool industries.

2. Publish standards for IPL. The current PDK technology is a ''0.1 draft standard,'' said Jingwen Yuan, strategic alliance manager at Synopsys. There is a push to devise version 1.0 of the technology, Yuan said.

3. Develop reference documentation for iPDK.

4. Devise standards for the analog constraints.

5. Grow the IPL alliance membership.

6. Demonstrate that the technology works. Last week, IPL members demonstrated the development of a 90-nm voltage-controlled oscillator (VCO). This was based on a generic 90-nm process, Yuan said. The device was being developed with various EDA tools in different locations worldwide. The design flow involved the development of a PDK using a custom design tools from Synopsys, a layout tool from SpringSoft, a design-rule checker from Mentor, a routing tool from Pyxis, among other steps.

The IPL Alliance was started in 2007, with five founding members: AWR, Ciranova, SpringSoft, Silicon Navigator and Synopsys. Mentor Graphics and Pulsic joined as supporting members. Today, IPL Alliance members include 13 major EDA and foundry companies. The newest members are: TSMC, Helic, JEDAT, Magma, Micro Magic and Virage Logic.

''While digital design automation has moved forward with amazing speed over the last 20 years, analog automation has lagged far behind. With RF and consumer devices demanding increased integration, the analog portion is now the gating factor on many, if not all SoC designs,'' Yuan wrote in a white paper.

''The custom design ecosystem needs a standard for process design kits (PDKs),'' she said in the paper. ''Interoperable PDK is based on the OpenAccess database and uses standard languages such as Tcl and Python that ensure interoperability among all EDA vendor tools. These interoperable PDKs include a comprehensive set of APIs to enable customization, support advanced PDK features and provide an interactive environment for PDK development.

''PCells written in Python (PyCells) not only have significantly fewer lines of codes, but also provide tremendous performance improvement compared to relative object based SKILL PCells (from Cadence),'' she said. ''PyCells support advance features such as abutment, stretch handles and DFM rules. PyCell Studio from Ciranova and IDE provide interactive environment for PyCell development and efficient PyCell debugging therefore improve PCell development productivity and shorten PDK development cycle. High-level Python APIs provides process porting capability within PDKs.

''No need to code PyCells for different process, just swap out tech files. This has great benefits for IP groups. When it comes to PDK validation, because interoperable PDK is based on OA, no stream-in or stream-out or any shape of data translation is needed among all leading physical verification tools. This makes PDK validation effortless,'' she added.

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