Teaching old dogs new serial I/O tricks on CompactPCI

by Barbara Schmitz, MEN Mikro Elektronik GmbH , TechOnline India - April 20, 2011

The new CompactPCI Serial standard (labeled CompactPCI-S.0), approved in March 2011, addresses new applications for system boards and backplanes. But like CompactPCI PlusIO, it allows the merger of existing CompactPCI parallel bus peripheral boards with new peripheral boards using a point-to-point star architecture capable of faster communication and higher signal density.

Even systems that have withstood the test of real-world applications for a decade or more are eventually challenged to keep up with the times. And popular CompactPCI systems used for robust, modular embedded

computing system applications in telecommunications, industrial automation, real-time data acquisition, instrumentation and military systems are no exception.

Until recently, CompactPCI systems were limited to a parallel bus and could not take advantage of high-speed serial point-to-point communications. Now, there are two new standards addressing implementation of such capabilities, with each offering a slightly different execution. But both offer similar benefits in terms of expanded high-speed I/O capabilities and performance.

The approved PICMG 2.30 specification for the CompactPCI PlusIO standard provides options for enhancing existing CompactPCI installations with the addition of high-speed serial communications.

It takes advantage of the user pins on the J2 connector that were originally designated for 32-bit system slots as a means to deliver serial signal capabilities, yet still maintains interoperability with existing CompactPCI systems.

This creates the option for a natural migration that still protects the capital investment in existing backplanes and peripheral I/O boards still using parallel bus communications.

The new CompactPCI Serial standard (labeled CompactPCI-S.0), approved in March 2011 by a PICMG sub-committee and announced at Embedded World, addresses new applications for system boards and backplanes. But like CompactPCI PlusIO, it allows the merger of existing CompactPCI parallel bus peripheral boards with new peripheral boards using a point-to-point star architecture capable of faster communication

and higher signal density.

 

Extending the capabilities of existing CompactPCI

CompactPCI PlusIO complements the original basic CompactPCI standard (PICMG 2.0), staying true to most of its mechanical requirements. To maintain reverse compatibility, new CPU boards that support PICMG 2.30

(3U/6U) remain fully compatible to the basic CompactPCI standard without limitations and can also be used in existing CompactPCI systems.

The original CompactPCI standard called for a single 220-pin connector to provide all power, ground, 32-bit, and 64-bit PCI signals. That connector consisted of two halves – the lower half (110 pins) called J1, and the upper half (also 110 pins) called J2. Backplanes used male (pin) connectors and plug-in boards use female (socket) connectors.

User I/O pins were not defined by the PICMG 2.0 standard. In order to support serial communications interfaces, however, CompactPCI PlusIO does identify specific assignments for the J2 connector user pins that

were reserved for 32-bit system slots in the original standard.

CompactPCI PlusIO uses these I/O signals to provide a variety of popular interface options to the backplane:

* 4 PCI Express x1 links
* 4 SATA
* 4 USB 2.0
* 2 Ethernet 1000Base-T

It can also support four PCI Express type 2 peripheral boards.

Hybrid rack systems are already commercially available with a slot to accommodate an existing CompactPCI PlusIO system board, three slots for existing CompactPCI peripheral boards and four slots devoted to

CompactPCI Serial peripheral boards. (Figure 1 below.)

 

                           

 

                                              Figure 1. CompactPCI.PlusIO Architecture.

 

Making a whole new connection to serial I/O

Maintaining compatibility with the original CompactPCI mechanics was an important goal for both the CompactPCI PlusIO and the CompactPCI Serial specifications. But in order to achieve the higher level demands of serial communications, something had to change along the way. That  “something” was the board connector.

The heart of the change outlined in PICMG 2.30 is an Ultra Hard Metric (UHM) connector with specific features to accommodate the performance demands of high-speed serial communications signals. Yet, that newly specified UHM connector remains physically compatible to mate with the hard metric headers currently used in the original CompactPCI system backplanes, so it can work in legacy systems.

Because the hard metric headers could not support high-speed differential signals like PCI Express or SATA, the UHM connector incorporates specific physical features to accommodate the needs of the higher data transfer speeds – up to 5 Gbit per second – without crosstalk. These include individually shielded pins as well as 100 Ohm impedance suited for transmitting single-ended as well as differential signals. (Figure 2 below.)

 

                                                       

 

                                                 Figure 2. UHMconnector

 

New options on the horizon

With both CompactPCI PlusIO and CompactPCI Serial already adopted, the embedded industry has already seen the introduction of commercially available boards for immediate implementation.

Where CompactPCI PlusIO is used for migrating legacy systems to serial connections, CompactPCI Serial is implemented for new systems designs built solely on serial technology, while remaining backward compatible
to older versions of CompactPCI.

The key advantages of CompactPCI Serial are that it is based on proven mechanics, can be mastered easily and is both reliable and robust – providing a high-tech solution with low cost and minimal overhead.

CompactPCI Serial is the only standard for modular computers that unites PCI Express, Ethernet, SATA and USB 3.0 on the backplane. The star topology architecture in the CPCI-S.0 specification simplifies the cost
and effort required for implementation by eliminating the need for additional hardware like switches, bridges or fabrics.

The CPU chipset at the heart of the system controls peripheral devices and components through point-to-point connections. This allows high data rates without forcing any device to concede bandwidth to another.

System designers have flexibility in how they choose to implement the new connectivity.

One option is a standard, fully-CompactPCI Serial system with nine slots via a one-slot CPU, since the CPU slot can accommodate eight peripheral slots. A dual-slot CPU allows a designer to combine both CompactPCI
Serial and CompactPCI PlusIO to create a hybrid system. Another iteration of a hybris system is connecting a CompactPCI system to Serial system via card pair. A dual-slot CPU system can include support for:

* 8 x PCI Express (also gen.3) (for local extensions)
* 7 x 4 lane interfaces
* 2 x8 lanes interface fat pipe with 2 dedicated I²C high-speed buses for the fat pipe
* Optional Serial RapidIO (SRIO)
* 8 x SATA/SAS (for hard drives and RAIDs)
* Supported by SGPIO bus (SFF-8485 specification) for hot-plug capability
* 8 x USB (also 3.0) (for hot-pluggable mobile I/O as a legacy interface)
* 8 x Ethernet (also 10 Gb) (for computer-to-computer connections)

 

                                  

                                                             

 

Figure 3a CPCIPlus Star

 

Optional hot-plug support by one dedicated I²C bus and optional IPMI support by one dedicated I²C bus are also available. The accommodation of USB 3.0 interfaces supporting Gigabit/second bandwidth offers ten
times the bandwidth of the USB 2.0 format supported by CompactPCI PlusIO. (See Figure 3a, above and Figure 3b below.)  

     

 

 

Figure 3b. CPCIPlus_Mesh 

 

 

As shown, each CPCI-S.0 peripheral slot has the ability to support:

• 1 x PCI Express interface
• 1 x SATA (supported by a dedicated SGPIO bus – SFF-8485 specification)
• 1 x USB 2.0
• 1 x USB 3.0
• Up to 8 Ethernet interfaces
• Geographical addressing

For simplicity and versatility, every slot defines identical interfaces, with the CPU distributing the signals to each of the eight peripheral slots via the backplane. CompactPCI Serial’s star architecture ensures that one system slot can control up to eight peripheral slots, with no bridges, switched fabrics or special backplanes required.

One dedicated PCI Express fat pipe is provided for high-end applications and two of the slots support an additional PCIExpress x8. Otherwise all peripheral slots are equal in the sense that any board can be plugged
into any slot. 

A full-mesh architecture for Ethernet applications supports up to nine boards (eight peripherals plus one system board) with no bridges, switched fabrics, or special backplanes required.

It is much easier to build multi-processing systems based on Ethernet, and the system slot is no longer a potential single point of failure, since every board can communicate with every other board directly without a switch (full-mesh).

The Ethernet is based on 100/1000/10GBaseT standard. Boards are non-reactively coupled and optimized for symmetrical multiprocessing and redundant systems.

Board and backplane dimensions, front panels, and hot-plug mechanisms for CPCI-S.0 are identical to and fully compliant with PICMG 2.0. The specification is also compatible to IEEE 1101 and can accommodate standard 19-inch racks. This guarantees that mezzanine modules that have been designed for these boards – and which are indirectly based on the IEC1101 standard – are also compatible with the CompactPCI Serial standard.

Unlike the modified connector configuration used in CompactPCI PlusIO, the CPCI-S.0 connector is an entirely new design supporting more pins capable of operating at higher frequencies.

This enables higher signal density and supports transmission frequencies of 12 Gbs/second. Also, contrary to CompactPCI and CompactPCI PlusIO, the male-pin plug is mounted on the module and the female receptacle is on the backplane, as it is in VMEbus systems.

This arrangement is a more rugged construction than legacy CompactPCI and eliminates the concern of twisted pins on the backplane. In the event that a connector pin does fail, the plug-in card can be replaced instead of the whole system backplane. The new CompactPCI Serial connector design is also better prepared for harsh environments, with walls on all four sides.

Depending on the function of the board, there are a number of ways those connectors might be assembled. For example, a peripheral board in 3U format equipped with only one connector at the backplane can save costs.

However, using multiple modular connectors positioned next to each other on a larger board can not provide the same rigidity as a single larger connector that would help to stabilize the board mechanically. For CompactPCI Serial’s use in rugged applications, an additional element has been introduced – the guide element – for guiding, holding and stabilizing the plug-in card on the backplane.

This way, a 3U assembly is also guided in the middle of the backplane, even when only the lowest connector is assembled. With the guide element, shock and vibration resistance are improved because the PCB cannot bend.

An ancillary benefit of CompactPCI Serial lies in the potential for hot-swapping peripheral boards during operation without damaging them and without disturbing the function of the computer.

The ability to accomplish this with several simple measures in a 19” system complying with IEC 1101 offers advantages for multiple real-world circumstances such as a pluggable hard disk, RAID systems or complex
multiple systems.

 

One concept, two standards, multiple interfaces

With their dedication to enhancing the CompactPCI concept without rendering it obsolete, both the CompactPCI PlusIO and CompactPCI Serial standards accommodate the use of previously designed CompactPCI peripheral boards in upgraded applications.

While the CompactPCI Serial slots are best suited for functions like 10 Gigabit Ethernet or high-end graphics with high data-rate requirements, the parallel CompactPCI bus still delivers acceptable performance for
many types of conventional I/O such as binary or analog signals. This best-of-both-worlds scenario is a rare commodity in the rapid-turnover world of computing technology.

It provides CompactPCI users with a migration path that helps them maintain the value of past equipment investments by opening up new avenues to high-speed communications capabilities that could extend the
practical life of existing systems investments by up to 15 years.


About the Author:

Since 1992, Barbara Schmitz has served as Chief Marketing Officer of MEN Mikro Elektronik. She graduated from the University of Erlangen-Nürnberg. Later, she studied business economics in a correspondence course at the Bad Harzburg business school and followed an apprenticeship in Marketing and Communications in Nuremberg.

 

 

 

 

 

 

 

 

 

 

 

 

 

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