e-MMC vs. NAND with built-in ECC

by Doug Wong , TechOnline India - August 23, 2011

Ultimately, if your processor can support both e-MMC and MLC NAND with ECC, which should you choose? A look at the attributes, benefits and situational advantages of each

As NAND flash continues to increase in density and decrease in cost per gigabyte, it has enabled more cost-effective storage. This benefits a wide (and constantly growing) range of digital consumer products. Selecting the most appropriate high performance NAND architecture for any given application is of

increasing importance as the ECC requirements for NAND continue to increase.

This article will explore the attributes of and differences between e-MMC and NAND with built-in ECC (such as Toshiba’s SmartNANDTM) – as well as go into detail about the applications that are best suited for each.

Exhibit A: e-MMC

First up, e-MMC, which stands for embedded multimedia card, is one of the most popular embedded memory solutions.  It consists of a number of NAND flash memory devices and a controller in a single ball grid array (BGA) package.  It is used in a variety of mobile applications such as: smartphones, digital book readers, and portable terminals.  e-MMC is a widely-supported JEDEC standard that uses the HS-MMC (high speed multimedia card) interface and command protocol.

The e-MMC is the embedded (chip) version of the multimedia card.  Originally created by Siemens and Sandisk, it has evolved to become one of the most widely available standard non-volatile memory devices for embedded use.  

The JEDEC e-MMC standard V4.41 has backward compatibility. Therefore, it is possible to operate
a V4.41 compliant device on a V4.3 or V4.4 compliant system. Several security functions such as Secure Erase, Secure TRIM, and RPMB are added to V4.4 compared to V4.3. Moreover, the Hardware Reset Signal and DDR interface became available for V4.4 onward. Furthermore, new functions such as HPI, background operation, write reliability and enhanced reliable write are added to V4.41.  The table
below is a comparison that shows the differences between JEDEC standards V4.3, V4.4 and V4.41.

                                   

Composition of an e-MMC System

An e-MMC system generally consists of a host controller, an e-MMC device, and a HS-MMC driver, which is software that controls the e-MMC (see Figure 1).

1. The host controller has a host CPU and a HS-MMC interface. The e-MMC also has a HS-MMC interface.

2. The e-MMC consists of raw MLC NAND flash memory and a controller. The controller has a HS-MMC interface which can be connected to the host controller. It also has a NAND interface which is connected to the raw MLC NAND flash memory. It has several functions such as bad block management, wear leveling and error correction code (ECC), to utilize the raw MLC NAND flash memory efficiently.

3. The HS-MMC driver handles operations between the host controller and the e-MMC.

                                          

 

                                                          Figure 1: e-MMC System Architecture

Advantages of an e-MMC System

The primary advantage to using e-MMC, as compared to using raw NAND or NAND with built-in ECC, is that it is a fully managed solution.  This means that all NAND flash management is handled by the
internal controller.  The host does not have to manage the primitive operations of the NAND flash such as wear leveling, bad block management, ECC, and logical-to-physical address translation.

Just like a hard disk drive, the e-MMC acts like an ideal block device.  The host can read and write and
overwrite logical address locations without the need to do the erasing that is necessary when dealing with raw NAND flash memory or NAND with built-in ECC. 

The addressing is by logical address, so there are no addressing gaps issues, no need to deal with bad physical blocks, and no need for the host to maintain logical-to-physical address lookup tables.  Wear leveling, the spreading of  writes to different physical blocks (to avoid concentrated writing to specific
physical blocks), is handled automatically by the internal controller.

e-MMC is easy to use and widely available.  Compared to using raw NAND or even NAND with built-in ECC, it frees the user from having to develop their own or purchase the required NAND flash management software.
 

Exhibit B:  NAND with built-in ECC

NAND with built-in ECC also consists of a number of NAND flash memory devices and a controller.  It is available in both an LGA (land grid array) package, as well as a TSOP (thin small outline package). This architecture uses the industry-standard physical interface of raw SLC/MLC (single level
cell/multilevel cell) NAND flash memory, but adds additional commands and built-in error correction.  It is basically NAND flash with internal error correction circuitry. 

NAND with built-in ECC uses the industry-standard asynchronous raw NAND flash interface.  By incorporating built-in error correction, it enables systems that could only support the ECC requirements of  SLC NAND to use MLC NAND flash, which enables systems to achieve lower cost per bit and higher densities.  The command set is a superset of the standard NAND flash commands, enabling easy adoption of NAND with built-in ECC into existing systems which already support NAND flash.

In addition to the standard (MLC) mode, this architecture also offers a reliable mode (pseudo SLC) for
enhanced speed, reliability, and endurance.


Composition of a NAND with built-in ECC System

A NAND with built-in ECC system consists of a host with a NAND interface, the memory device which has NAND with built-in ECC controller, and the memory device driver (see Figure 2).  Both NAND
flash and NAND with built-in ECC require upper layer device management in the form of flash translation layer software or a flash file system.

 

1. The host controller must have a NAND flash interface.

2. NAND with built-in ECC consists of raw MLC NAND flash memory and a controller. The controller handles the error correction and presents a standard NAND flash interface to the host.  However, the controller does not perform higher level functions such as bad block management, wear leveling and logical-to-physical address translation.

3. The driver handles operations between the host controller and the device.

 

   

                                                 

 

Figure 2: NAND with built-in ECC System


Advantages of a NAND with built-in ECC System

Many embedded processors already support the standard asynchronous NAND flash interface, so using NAND with ECC is relatively easy and usually only some minor driver development is necessary.  The biggest advantage to using NAND with ECC is the fact that most general purpose processors lack the
hardware error correction circuitry necessary to utilize the latest generation of multi-level cell NAND flash memories.  The level of error correction required to use the latest generation of flash memory is now 30-40 bits per kilobyte. 

Other than specialized NAND flash memory controllers like USB controllers, SD card controllers and SSD controllers, few processors have such dedicated hardware ECC blocks.  Therefore, most general purpose processors have been unable to support and use the latest MLC NAND flash devices.  By moving the ECC circuitry into the NAND package, processors with limited or no ECC hardware can
take advantage of the higher density and lower cost per bit of MLC flash.

 

The Choice Between e-MMC and NAND with built-in ECC

The performance of either product is hindered by the characteristics of the MLC NAND memory internal to the devices.  Thus, the interface speed has less of an effect.  The e-MMC has the advantage in terms of  the interface speed (double data rate (DDR) mode in V4.4 at 52 MHz equals 108 MB/s versus 33 MB/s for NAND with built-in ECC).  However, interface speed is not the whole story.  For many users of raw NAND, the lower maximum latency and control over NAND operations offers a real performance advantage versus a fully managed solution.  In a fully managed solution such as e-MMC, all firmware that manages the NAND flash (wear leveling, block management, address translation,
garbage collection) is running on a relatively low-horsepower microprocessor. 

The RAM buffer space available is quite limited.  On the other hand, the host processor is more likely to be a high-performance processor with significant RAM resources available to it.  Running an optimal flash file system on the host could be significantly faster.  Due to the limited RAM (and cache) available on e-MMC, random access operations tend to be significantly slower than in processors with significantly more RAM, such as SSD controllers.  But for large sequential read and write operations, the performance of e-MMC can be excellent: speeds in excess of 30 MB/s can readily be achieved.  Therefore, e-MMC works very well in mass storage applications in which large files are being transferred.

However, as portable systems become more PC-like in their operation and the operating system is juggling multiple programs, access patterns are becoming more random.  In these situations, a lower latency memory solution is desirable for high performance.  In the latest versions of the e-MMC spec, V4.4 and V4.41, the high-priority interrupt command was introduced to allow the host to interrupt the long busy time associated with writing and garbage collection.  Users of raw NAND have had much more control over time-consuming operations such as wear leveling and garbage collection through
host-run flash management software.  There is boot support in e-MMC, but many systems do not yet take advantage of the feature.  Systems that boot from raw NAND might be able to also boot from NAND with built-in ECC, but since the device IDs are different, some modifications may be necessary.

Usually, the choice is decided by the availability of interfaces on the chipset chosen.  If there is an e-MMC/SD card port available, then e-MMC is often the choice.  If there is a NAND port available, then NAND with built-in ECC might be chosen.  NAND with built-in ECC is a good choice for a system moving from SLC to MLC for higher density and lower cost.  It is an alternative to e-MMC if better random access performance is needed, but significant software development might be required to implement flash memory management.  The cost difference between the two is likely to be negligible, although NAND with built-in ECC theoretically should be slightly less expensive due to a less complicated controller.

Applications: Specific Instances Where One System is Preferable Over the Other

Ultimately, if your processor can support both e-MMC and MLC NAND with ECC, which should you choose?  It really depends on the access pattern expected in your application.  If the access pattern is relatively long and sequential, i.e. relatively large block transfers, then e-MMC will give you excellent performance and relieve you from the burden of using NAND flash management software.  Since the performance of reads and writes for this type of access pattern is largely limited by the NAND flash performance itself and not the controller, then there would be little performance difference between using e-MMC vs. MLC NAND with ECC.

However, many systems are becoming increasingly sophisticated and are running multi-tasking operating systems on multi-core processors.  These types of systems generate a much more random
access pattern to the storage memory due to the multiple executing threads of software code.  In this type of situation, a storage system like a solid state disk drive can offer the performance required due to the large cache size. Since many systems already have a large amount of DRAM onboard, if the applications
processor is powerful enough, the effective performance of an SSD could be achieved using MLC NAND with ECC using the appropriate NAND management software running on the host.  In effect, one would be creating a “soft” SSD using the host’s resources.  In comparison, the RAM available for caching inside the e-MMC controller will always be more limited due to space (it must fit on the
controller die and is usually SRAM), and the controller inside the e-MMC may be significantly lower in performance than the host processor.  Therefore, smart devices -which are essentially high performance, multi-tasking computers - could see performance advantages in using MLC NAND with ECC vs.
e-MMC.


Summary

When system designers consider using MLC NAND flash as the non-volatile memory in their system, they can choose either raw MLC NAND flash (if their controller can support the ECC requirements), e-MMC, or MLC NAND with ECC.  Few general purpose processors can support the latest generation of MLC NAND flash because their hardware ECC engine cannot support the latest bit correction requirements.  e-MMC has been a very popular solution in many embedded systems and provides ideal block device behavior by doing all of the required flash management necessary using internal firmware.  However, there are systems that can benefit in performance through the host-directed management of NAND flash operations, and the newly available MLC NAND with built-in ECC devices, like Toshiba’s SmartNAND, offer users the option of using the latest MLC NAND flash devices while managing the read, program, and erase operations just like raw SLC/MLC NAND flash.


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* e-MMC is a trademark of the MultiMediaCard Association.
SmartNAND is a trademark of Toshiba Corporation. All other trademarks and tradenames held within are the properties of their respective holders.


About the Author:

Doug Wong – Senior Member, Technical Staff for Toshiba America Electronic Components, Inc. – As a Member of the Technical Staff for TAEC, Mr. Wong’s responsibilities include system engineering and new product definitions for NAND flash memory, explaining their characteristics, functionality and use to design engineers, writing applications notes and technical documentation, solving customer engineering problems and fielding technical questions.  He holds a BSEE degree from California
Polytechnic State University, San Luis Obispo, and a MSEE (semiconductor physics concentration) from University of California at Los Angeles.

                             

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