Meet the SERDES challenge: Design a high-speed serial backplane

by Dr. Michael Heimlich , TechOnline India - October 12, 2011

Having high-frequency design tools resident on a VNA streamlines design and addresses the SERDES challenge.

The benefit of having high-frequency design tools resident on a vector network analyzer (VNA) does not become obvious until the time comes to compare simulation to measurements. At this point, the advantage of a more streamlined work flow -- without the impediment of transferring data to a simulator running on a separate PC or workstation - becomes clear. To illustrate the benefit of such an approach, this article follows the design flow for a high-speed serial backplane.

BACKGROUND: THE SERDES CHALLENGE

Increasing chip-to-chip, board-to-board, and system-to-system communications data rates have created the need for multi-gigabit asynchronous signaling schemes in which serializer/deserializer (SERDES) technology is used to format and transfer data. Analysts predict that SERDES I/O data rates will double every two to three years, so speeds in excess of 8Gb/s are already on the way and placing the SERDES design challenge clearly into the microwave domain. Consequently, designers familiar only with lower-speed buses will now be facing new physical and electrical design challenges.

For example, with SERDES, bit error rate (BER) must be maintained at 10E-12 or below, yet the loss incurred by low-cost packaging, printed circuit board, and backplane materials increases with frequency. In addition, mismatch, coupling, dispersion, and other RF effects degrade the quality of the channel connecting the transmitter to the receiver. Consequently inter-symbol interference (ISI) and crosstalk simulations must use accurate modeling that includes analog, RF, and electromagnetic (EM) effects. Microwave quality models of the channel are also necessary in order to capture the effects of dispersion and coupling.

In an ideal world, a serial channel model based upon a combination of both measurement and simulation

would ensure compliance within manufacturing tolerances. Thankfully this ideal is realizable today with AWR’s Microwave Office software embedded onto the Anritsu’s VectorStar VNA (The VectorStar family is Anritsu’s Premium VNA line. The MS4640A Series offers the best performance covering a span of 70 kHz to 70 GHz.)

 

 

 

 

Figure 1. High-speed serial backplane board design as depicted in AWR’s Microwave Office software installed on the Anritsu VectorStar.

 

SERDES DESIGN EXAMPLE

For this SERDES example, a VNA with four measurement ports is required as the signals are differential pairs rather than single-ended and on the four-layer board, one channel requires two input and two
outputs. Nonlinear simulation within the Microwave Office software is required to view the eye diagram as a measure of channel quality. This also requires a pseudo-random bit stream (PRBS), which is a voltage-variable signal in time and outside the realm of linear simulation.

 

 

 

Figure 2. SERDES PCB Design of microstrip, stripline, and coplanar single-ended and differential channels using predictive schematic elements and verified with AXIEM.

 

 The demonstration SERDES board created for example is 12”x12” and comprised of Nelco N3000si materials - given its high-speed and broadband capabilities. Two channels of the microstrip and stripline were developed with the goal of creating both “good” and “bad” channels for comparison sake. The initial design was created in Microwave Office software performing linear simulation with microwave models that were used to automatically lay out the channel. It was extracted into AWR’s AXIEM 3D planar EM simulation software to more accurately characterize the transitions. For design verification, AWR’s APLAC harmonic balance simulator was used to generate eye diagrams in order to ultimately achieve the best eye opening scenario.

 

 

Figure 3. Complex structures can be analyzed and viewed in 3D with a combination of circuit- and system-level simulation, including S-parameters, eye-diagrams and bit-error rate (BER).

The linear test, in this case, was a four-channel measurement with differential signaling, mixed-mode S parameters rather than single-ended S parameters.Although the design was created using linear models and simulation was performed with AWR’s AXIEM EM solver, a harmonic balance or time-domain (SPICE-like) simulation was required to view nonlinear performance.

The entire AWR design environment was running on the Anritsu VectorStar. The PRBS was increased to 20 Gb/s to see where the transitions in performance appeared. The simulation showed the PRBS nonlinear signal source driving a measured device with Microwave Office running on the instrument while it was itself measuring the channel.

Summary

The ability to perform high-frequency circuit simulation and simultaneously take measurement data of a circuit using a single “workstation” has benefits in many circumstances, and invariably saves time. For high-speed PCB design in particular, it is highly desirable to be able to achieve initial, good channel design before further steps in the development process proceed. The addition of drivers and receivers to the design increase not only complexity but costs. To perform validation of the growing design complexity with the same nonlinear signal sources with which it was designed and to simultaneously take the requisite measurements too is the value-add with AWR Connected for Anritsu VectorStar.

About the Author:

Dr. Michael Heimlich is a professor at University of Macquire in Australia and an AWR technical consultant.


 

About Author

Comments

blog comments powered by Disqus