Using in-design physical verification to reduce tapeout schedules

by Tadahiko Yamamoto, Norikazu Ooishi, Toshiba Corp., and Kerstin McKay, Synopsys Inc. , TechOnline India - August 04, 2010

Physical designers moving to lower foundry nodes worry about how to verify and deliver a design that is free of DRC violations while meeting their tape-out schedule. This can be quite challenging given that the number and complexity of DRC rules is increasing and designs are getting bigger. The need for a better understanding of the manufacturing issues during the design phase raises concerns about how to best address these issues.

Physical designers moving to lower foundry nodes worry about how to verify and deliver a design that is free of DRC violations while meeting their tape-out schedule. This can be quite challenging given that the number and complexity of DRC rules is increasing and designs are getting bigger. The need for a better understanding of the manufacturing issues during the design phase raises concerns about how to best address these issues.

Synopsys' IC Validator, combined with IC Compiler, provides both the functionality and performance required for an in-design physical verification solution. This paper highlights the advantages of using IC Validator at several stages of the Toshiba design flow for both DRC and metal fill. Toshiba demonstrates the runtime and flow benefits of using IC Validator to find and debug DRC issues during the implementation stage. Toshiba also shows a significant reduction in total schedule time for completing DRC and metal fill using IC Validator.

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