# Reducing signoff corners to achieve faster 40-nm SOC design closure

TechOnline India - January 03, 2012

This article describes what has been done to reduce the timing sign off corners through a better understanding of the smaller geometry variations across multiple corners and how it affects equally good silicon quality.

In the race to achieve high design performance and stringent power requirements, the VLSI world is moving quickly down the scaling curve to process technologies that enable transistor fabrication at smaller and smaller geometries: 40nm (C40), 28nm, 20 nm and so on.

As we go down the technology nodes, a lot of new design variable comes into picture, causing our previous assumptions to fail. This has the result of forcing the use of more timing signoff corners to be take into account their variations at different PVT (Process, Voltage and Temperature) values.

For example, we may have as many as 16 timing sign off corners at C40, thus drastically increasing the turnaround time for the SOC implementation and closure.

In this article we describe what we have done to reduce the timing sign off corners through a better understanding of the smaller geometry variations across multiple corners and how it affects equally good silicon quality. Our analysis indicates that it is possible to reduce the design cycle closure time significantly with only a slight increase in sign off uncertainty.

Accurate Timing Analysis with Corner Definition

An SOC is mainly comprised of millions of sequential elements with combinational cells connected through metal nets which generates a number of timing paths (Figure 1, below). For an SOC to work properly, all the timing paths have to meet certain special timing checks like setup, hold (or any other race condition) etc.

Figure 1: An example of a timing path

Suppose you want an SOC to work at some particular PVT setting determined by specific set of process, voltage and  temperature range values. Temperature range comes from the application requirement and can be as extreme as -40 C to 150 C. Depending on the voltage regulation specs used to derive the SOC constraints and taking into account the other voltage drop effects across the SOC, the voltage range is the first thing that must be determined (for example, 1.08V to 1.32V). The process which determines the quality of silicon doping has a strong dependency on the manufacturing capabilities of the silicon fabrication units.

Depending on the PVT conditions, gate delays and net delays can vary. Silicon designers need to ensure that the SOC’s should work across all the PVTs. This can be done by checking the timing requirements on all the timing paths at different PVT conditions.

Variations and their effects

Process, voltage and temperature are individually responsible for making the silicon gates act differently. A particular process value which determines the gate silicon is doped properly (a good process) is needed to provide best delays. With high voltages, gates get charged or discharged quickly, providing faster delay.

As temperature decreases, majority charge carriers collide less often, making the silicon gates respond more quickly, resulting in lower delays. On smaller technology nodes, after a threshold is reached, the Temperature Inversion Effect can introduces the reverse effect, with the result that gate delays can vary in opposite direction to temperature effects.
At higher geometry process nodes, such as 250nm, 130nm it was enough to consider two corners - worst & best - where the effect of temperature inversion was not prominent. But at C90 geometries and smaller the silicon quality may demand two more corners, such as best-hot & worst-cold.

Summarizing the above and converting this into an SOC spec we can now introduce the following four corners to define the silicon variation. (For example, an SOC voltage range of 1.08V - 1.32V and a temperature range of -40C to 150C). This is shown below in Table 1.

Table 1: Corner definition with PVTs

Interconnect variation

Each metal interconnect wire - depending on its dimensions - contributes its resistance and capacitance values to such things as delay. The interconnect delay of a net, which is the combination of several metal wires and VIA connections, are modeled in the form of RC networks.

For the 90nm and higher process technologies, the interconnect delays doesn’t contribute much towards the timing path delay nor did the variation of net delays. Even C-Max (C max & R min) and C-Min (C min & R max) corners were enough to cover all silicon variation.

But as the technology shrinks toward smaller nanometer regimes, interconnect delay becomes more dominant compared to gate delay. At this point, calculating interconnect delay is more crucial and plays a major role in achieving an accurate timing check. The result: two more RC corners must be introduced - Delay Corner (R x C maximum, Cc minimum) and Crosstalk corner (R x C minimum, Cc is maximum). Temperature also becomes a key factor in interconnect variation.

Timing Signoff Corners

Combining silicon variation and interconnect variation we have following 16 applicable corners for timing signoff, as shown in Table 2, below.

Table 2: Sixteen (16) signoff corners

Usually for setup timing checks, it is quite easy to determine the signoff corners. But at each process shrink, hold checks are critical in every corner because of a direct linear dependency on clock skew. As a result, to make an SOC work for all PVT values, it is necessary to check “holds” on every defined corner.

Quality versus time to market

To meet achieve the best performance in an SoC design at smaller geometries, then, it is necessary to do timing sign off in all the 16 corners. But with this many corners, the iterative execution process of silicon design not only slows down, but becomes so complex that current EDA tools might not be up to the management task. This has direct impact on the time to market.

In today’s demanding world where quality and time to market are of equal importance it is very important to understand the impact of process technology variation. What is desirable is to come up with improved sign off criteria and a reduction in the number of sign off corners. This opens up the possibility of faster SOC closure, which nonetheless meet the required silicon quality in all 16 corners.

Corner Selection Methodology

For timing sign off setup and hold timing requirements to be met at all the corners, a setup corner selection method needs to be chosen in which the data path logic is simple and easy to identify. Hold timing being dependent on clock skews becomes critical in every corner. Following is a discussion of the methodology we think is needed to reduce hold sign off corners at C40.

Hold Timing. The hold timing requirement demands the minimum required delay in the data path so that previous data on the capturing flop can be transferred correctly as shown below in Figure 2 below.

Figure 2: Timing Path with hold timing

If T(A) & T(B) are the clock latencies of launching & capturing a flop, D is the delay in data path & H is the hold timing requirement of capturing the flop. Then as per the requirement,

D >= H + [ T(A) – T(B) ]

Hold Uncertainty. To avoid variations introduced by other unknown parameters, designers must factor in an extra uncertainty with respect to each corner. So, if h is the hold uncertainty, then above equation becomes more pessimistic by a factor “h,”as noted below.

D >= H + [ T(A) – T(B) ] + h

Critical Path Selection

In our methodology, the hold timing check is done with double the hold uncertainty so as to cover the paths which may be in violation at one location in one corner, but are met in other corners. Basically, the idea is to cover all the end points which are timing critical in the analysis.

As a result, the critical path selection includes all the violating paths as well as the paths which are met by hold uncertainty.

Figure 3 below shows the path distribution based on their timing slack and the timing path selection for the analysis. Similarly, this same calculation is done in all corners with respect to their specific hold uncertainties.

Figure 3: Critical Path Selection

Timing violations are identified in all the 16 corners. Following is the table showing the number of hold violations in their respective corners.

Table 3: Critical Paths in all 16 corners

If we combined all the corners we would find 7,677 critical timing paths across all corners, which are distributed randomly across 16 corners. The idea is to come up with a solution by which we can identify particular hold corners which incorporate all the 7,677 timing paths.

Basic corner selection

Based on prior experience in the older technologies (250nm 180nm 130nm 90nm etc), a few basic corners can be marked compulsory and must be considered at timing signoff. They are WCS-HOT-Cmax, BCS-COLD-Cmin and BCS-HOT-DLY. With these three corners, it is possible to cover 4,998 unique violating paths, representing 65.1% of the total number of unique critical paths. This is shown in the Table 4 below, where Column 4 has been named ‘must’.

Selecting the next best corner. One by one all the remaining corners are clubbed with the above selected three corners, out of 13 possible combinations of four corners (3 above and 1 new). The combination which we think results in maximum coverage is then chosen for the next stage. For example, in our analysis as shown in Table 4 below, the column ‘Snapshot1’ shows that after clubbing BCS-COLD-DLY to the above criteria, the unique critical path coverage reaches 72.4 % covering 5,558 number of paths.

In a second run, the remaining 12 corners are clubbed one by one with the combination of four corners and we jump to next best corner. The above process is repeated again and every following run results into the addition of one corner and increased coverage of critical paths.

In Table 4, Snapshot 2 shows the third run where two more corners are clubbed, with a total of 6 corners providing 87.7 % coverage. The end of the above sequence depends on the quality quotient we want to achieve.

The final eight and the silicon quality

In Snapshot 3, after fifth run - when 8 corners are selected – coverage is increased to 97.3 %. Because of the diversity of hold paths at each different corner, the rate at which the unique critical path percentage increases with every new corner selection is slowed down.

At this point saturation occurs, and eight selected corners are marked as the ‘Final 8’. The above has given us the best possible combination of 8 corners, which in turn gives maximum coverage to assure the best silicon quality.

Adding robustness with increased sign off hold uncertainty

While the final eight corners covers 97.3 % paths, there is still a gap of 2.7 %, leaving more than 200 paths untested. To cover these violations, the hold signoff uncertainty is increased by 20 psec for worst corners and 10 psec for all corners. At this point, with increase hold uncertainty, all eight corners are re-checked to determine a new unique critical path collection to include the 7,660 critical paths of the original signoff runs in 16 corners. This analysis is shown in Figure 5 below.

Table 5: The Final 8 with New Hold uncertainty

Conclusion

The above methodology provides intelligent sign off corners selection results with only a slight increase in sign off hold uncertainty. But the total sign off corners have been reduced to eight, which makes the iterative execution process of silicon design much quicker. This makes it possible to achieve SOC closure and still meet the required silicon quality.

Ateet Mishra (Ateet.mishra@freescale.com) is a Senior Design Engineer at Freescale Semiconductor, India. He has 6 years of industry experience in various fields of VLSI, such as Static Timing Analysis, Physical design & Synthesis. He has been associated with Freescale since the beginning of his career and has successfully taped out multiple SOCs in various technologies ranging from 250nm to 40nm.

Rajiv Mittal (Rajivmittal@gmail.com) worked as Senior Member of Technical Staff in ASIC/Layout Design Team in India. With more than 11 years of experience he has worked in a wide range of SoC and ASIC design domains, mainly in physical design activities across a number of process technology domains, ranging from 130nm to 40nm.

Article Courtesy: EDA DesignLine