Processor architectures: Where will we will be in 2020?

TechOnline India - July 22, 2009

In the first of a series of "2020 Vision" forward-looking perspectives by Texas Instruments' leading visionaries, TI Fellow Gene Frantz looks at where processors will be by then.

I have come to the conclusion that too many of us have no clue where we are going with technology. Rather, we are just busily moving forward and don't know if we are even moving in the right direction. It would seem that with our extensive experience in traveling we would understand a basic concept " to travel to a distant place requires two points:

  1. Where I am
  2. Where I want to end up at

The same goes for technology " we need to know where we are going to move in the right direction. So, I have challenged several of our senior technologists to think about what the state of the art will be in the year 2020. You might say that we need to have 20/20 vision for the year 2020. I have invited a number of technologists to provide their point of view (POV) of what the state of the art in IC technology will be in the year 2020, and I'm interested to hear what you have to say on the topic. But, since this is my blog, I will have the first and last word on what the year 2020 will hold for us.

So, here are my first thoughts on the topic.

  • Processing elements will be single clock domains. After many years of assuming that Moore's law would give us faster and faster clock speeds, we have finally concluded that clock speed is no longer our friend. In fact, we should have noted that 15 years ago, but as we move forward, processing elements will be of the size that the CPU can communicate with all of its resources in one clock cycle.
  • Systems will be made up of multiple processing elements. Integrated systems will be made up of many heterogeneous processing elements, each being a "single clock domain" processor.
  • The processing elements will be arranged in a similar style as FPGAs today.
  • We will take advantage of the third dimension. Integration using stacked die techniques (SIP) will be just as common as fully integrated SoC.
  • All will be programmed with a high-level language. The development environment will have the ability to take into account all of the resources in the system. That is the microprocessors, DSPs, accelerators, peripherals, analog signal processors, analog peripherals, RF and other things I have forgotten about.
  • IC designs will consist of smaller teams (5 to 10 designers) taking a shorter amount of time (6 to 12 months) to do the hardware design. Reuse will be the norm. While I am at it, let me explain that there are two definitions of "Reuse":

    1. I'll do such a good job on my design that everyone after me will use it.
    2. I don't have time to reinvent the wheel, so I need to find something that is close enough to what I need to meet the schedule.

    Unfortunately we use the first definition more than the second. Small design teams with short schedules will require us to use the latter definition. And, yes, there are companies already adopting this concept of reuse.

  • The bulk of the innovation will be in the software on top of the hardware.
  • Hardware will become part of the platform on which innovative designers will develop their ideas.

So, this is a sketch of how I see 2020. After a couple of POV papers from others at TI, I will come back with a conclusion. My colleagues will dive into topics such as programmability, tools and SoCs in the next few blogs. If you would like to share your view of 2020 with me, please comment or send me a private note.

Gene Frantz is TI Principal Fellow, Futurist and Business Development Manager, DSP.

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