Power Intent Formats: Light at the End of the Tunnel?

by Sorin Dobre (Qualcomm), Pete Hardee (Cadence), Colin Holehouse (ARM), Minh Chau and Rolf Lagerquist (Texas Instruments) , TechOnline India - February 14, 2012

The methodology differences between the power intent formats - CPF and 1801-2009 and, due to UPF 1.0 backward compatibility, there are two methodologies within 1801-2009. As a result, the industry must address the methodology differences before any meaningful discussion can take place on power format convergence - we elaborate on a path to methodology convergence.

Abstract

Two widely adopted formats for power intent exist: Si2’s Common Power Format (CPF) and IEEE’s Unified Power Format (UPF). The formats have been described as the “same in every intent, but different in every detail.” The IEEE’s 1801-2009 specification, colloquially known as UPF 2.0, is the extension of Accellera’s UPF 1.0 specification and is a big step forward to be a more robust power format standard. However, the industry is experiencing pain that there are multiple formats and many engineers would prefer one. The differences are widely characterized as CPF versus UPF, but this is an over-simplification. The differences go beyond syntax or even semantics; some differences are actually inherent in methodology used to capture and implement the power intent. As a result, some would question whether format convergence will ever be possible.

There are methodology differences between CPF and 1801-2009 and, due to UPF 1.0 backward compatibility, there are two methodologies within 1801-2009. As a result, the industry must address the methodology differences before any meaningful discussion can take place on power format convergence. The authors elaborate on a path to methodology convergence that involves deprecating the incompatible methodology enabled by some UPF 1.0 constructs, such as power supply net–driven power intent specification; emphasizing the “successive refinement” methodology that is enabled by new extensions in 1801-2009 and is compatible with CPF’s layered power intent specification across different abstract levels; and, as 1801 has support for hierarchical design but CPF has a more formal hierarchical design approach, including macro modeling for power intent within hardened intellectual property (IP), that can be used to extend 1801.

The immediate benefit of methodology convergence is improved interoperability between different power formats in a mixed-format low-power design flow. Over the long term, the success of methodology convergence will lead to a fast track of format convergence. Standards process can often lead to a glacial rate of progress, but we believe this time will be different as the whole industry is aligned with the same objective and goal. Significant progress is underway toward methodology convergence. After five long years, we finally can see the light at the end of the tunnel. And for once it’s not an oncoming train.

Background: Design Techniques and Power Intent Standards

The need to deploy low-power techniques in system-on-chip (SoC) designs has accelerated greatly in the last few years, fueled by increasing performance demands and adoption of new very deep submicron CMOS process nodes. The need in battery-powered mobile equipment such as cell phones and digital cameras is obvious, but the advent of new categories of Internet-enabled mobile devices, such as smartphones and tablets, has recently accelerated the need. Less apparent to the casual observer is the rate at which home consumer electronics and high-performance computing segments are adopting advanced low-power design techniques. In consumer electronics, cost and quality are paramount. For equipment that is not battery-powered, while “green” design and power consumption per se are becoming more of an issue, with specifications such as Energy Star, low-power design is really about managing the thermal profile of the device. This reduces cost by reducing the need for expensive chip packages, heat sinks, and fans, and it improves quality in the form of reliability. Adoption of the latest process nodes is another widespread phenomenon, leading to the need to control increasing leakage power in designs across multiple segments. For this reason, it is commonly (and for the most part accurately) stated that at or below the 45nm node, all designs are low-power designs.

We can generally split the low-power design techniques into two groups: advanced and basic. By advanced low-power techniques, we mean using multiple, often switchable, power supplies. This entails splitting the design into power domains where each domain’s supply can either be shut off to reduce leakage, as in the case of power shutoff (PSO), also known as power gating; or the domains can be supplied with different voltage levels permanently, in the case of multi-supply voltage (MSV), or dynamically, in the case of dynamic voltage and frequency scaling (DVFS). Power gating can be implemented with or without state retention; that is, keeping some or all of the registers powered during shutoff to facilitate faster recovery when power is restored.

These advanced techniques cause a huge increase in complexity of both design and verification. They introduce many different power states, usually under software control. There are protocols that must be followed to successfully switch various parts of the design between power states, and have them switched off and brought back up when required without error. In addition to the functional design and verification needs this implies, there are many other needs we refer to as structural needs. Each power domain needs to be fully separated from other power domains, using appropriate isolators or level shifters on every signal that crosses the domains. These advanced techniques drove the need to express specifications and rules, requiring a set of design semantics not envisioned or supported by hardware description languages, which previously abstracted away power and ground connections during logic design phases as unnecessary facets of physical implementation. We refer to these power-related semantics as the design’s power intent specification. From this specification, the control logic and structure to implement the techniques can be derived.

The basic techniques have been used for a longer time, are generally well automated, and do not have the impact on implementation, verification, and design closure that the advanced techniques do. These techniques include clock gating and multi-threshold voltage (MVt) optimization, as well as logic synthesis tools’ ability to optimize power as a cost function alongside performance and area. These basic techniques generally do not require a power intent specification.

Over the last few years, the industry has adopted either of two leading formats―the Unified Power Format (UPF) and the Common Power Format (CPF)―for power intent specification. Accellera and the Silicon Integration Initiative (Si2) released UPF 1.0 and CPF 1.0 specifications, respectively, in early 2007 based on technical contributions from member companies. In 2008, UPF was handed over to the IEEE P1801 working group, who released the IEEE 1801-2009 standard, colloquially known as UPF 2.0, in March 2009. In this article, we use the term “IEEE 1801” to refer to the IEEE 1801-2009 standard. Meanwhile, the Low Power Coalition (LPC) of Si2 released the CPF 1.1 specification in September 2008 and CPF 2.0 in February 2011.

The Si2’s contribution of the Open Low-Power Methodology (OpenLPM) to IEEE, announced in May 2011, is a milestone in the development of power format standards and the most promising path yet for the industry to converge on one power format. Methodology convergence, however, is a pre-requisite for power format convergence. This paper explains what methodology convergence is required, and why the OpenLPM is a promising step toward enabling this convergence.

Fundamental Differences between UPF 1.0, IEEE 1801, and CPF

Although UPF 1.0 shares similarities with CPF, it has some fundamental differences in how the power intent is defined. Both specifications use structural groupings (called power domains) to refer to each collection of design objects sharing the same power supply. In CPF, power intent is primarily described by defining the power domain with implicit power supply starting at the register-transfer level (RTL). As the design flow evolves from RTL design to physical design, each power domain will eventually be refined into a primary set of power supplies to uniquely define this power domain. UPF 1.0, however, lacks such abstraction capability, so an RTL designer using UPF 1.0 has to describe the exact physical power network at RTL. The main difficulty of this approach is that RTL designers do not have the complete physical power network information. IEEE 1801 introduces the concept of supply set handles for the power domain, which has many similar properties to abstract power domain definition in CPF.

There are other major differences between UPF 1.0 and CPF, such as how the isolation and level-shifter logic between power domains is defined. Again, IEEE 1801 introduces constructs that close the methodology differences between UPF 1.0 and CPF in this regard (such as the way to specify isolation and level-shifter logic using the driving/receiving power domain or supply set of a signal).

In example of a simple design with two power domains. The top design has one external supply VDD and one of the internal blocks uses the switched version of the top supply VDD_SW, controlled by the signal pon at the top level.

Figure 1: A simple design with power gating

To describe Figure 1 using UPF 1.0, the power intent file would be as follows:

create_power_domain PD_blue –include_scope
create_power_domain PD_green–elements { I1 }
create_supply_net VDD –domain PD_blue
create_supply_net VSS –domain PD_blue
create_supply_net VDD_SW –domain PD_blue
create_supply_port VDD –domain PD_blue
create_supply_port VSS –domain PD_blue
connect_supply_net VDD -port VDD
connect_supply_net VSS -port VSS
create_supply_net VDD_SW –domain PD_green –reuse
create_supply_net VSS –domain PD_green –reuse
set_domain_supply_net PD_blue –primary_power_net VDD –primary_ground_net VSS set_domain_supply_net PD_green –primary_power_net VDD_SW \
–primary_ground_net VSS
create_power_switch PSW –domain PD_blue
    –output_supply_port { VDD_SW VDD_SW } \
    –input_supply_port { VDD VDD } -control_port { pon pon } \
    -on_state  { on VDD pon }  \
    –off_state {off !pon}

As indicated by the code above, designers using UPF 1.0 have to lay out almost the complete physical power structure at the RTL coding stage, which is not only a difficult task but also a completely unnecessary one. Using the power domain concept in CPF or the supply set construct in IEEE 1801, the power intent of the example design can be described easily at an early stage, as shown below:

Power intent in 1801:
create_power_domain PD_blue –include_scope
create_power_domain PD_green –elements {I1}
add_power_state PD_green –state off \
   {-simstate CORRUPT -logic_expr { !pon }}

Power intent in CPF:
create_power_domain PD_blue –default
create_power_domain PD_green –instances { I1 } \
   -shutoff_condition { !pon } \
   -base_domains PD_blue

It is clear that the methodology to describe power intent at RTL by using either CPF or the new constructs in IEEE 1801 is a much better approach than that of UPF 1.0. However, for backward compatibility reasons, IEEE 1801 includes all of UPF 1.0 and, as a result, there are two different methodologies to describe the same power intent within IEEE1801. Such a mix of methodologies in the same standard not only creates confusion for users but also adds unnecessary difficulties for tool vendors to support the standard. It is no surprise that two years after the release of IEEE 1801-2009, there is still limited tool support for the new 1801 methodology for power intent creation. This explains why designers who want to use IEEE 1801-2009 are pressuring vendors to support the true essence of the 1801-2009 specification, not just the UPF 1.0 methods. There are signs within both EDA and the user community that the momentum is finally shifting to facilitate this change. Figure 2 shows the current status of all power standards.

 

Figure 2: Current status of all power formats

 

Power Format Convergence Requires Methodology Convergence

To achieve full interoperability among different vendors supporting different power formats, the methodology differences between CPF and IEEE 1801 must be addressed. If the convergence of methodologies is complete enough and achieved relatively quickly, it could even pave the way for power-intent format convergence. Even without format convergence, methodology convergence would enable much easier support of two different formats for designers, IP providers, and EDA tool vendors. Methodology convergence has three main components:

1. Avoid the use of incompatible UPF 1.0 constructs and methods
2. Extend IEEE 1801 to include useful, commonly used CPF features as necessary
3. Extend CPF to include useful commonly used IEEE 1801 features as necessary

Note that even fully achieving all three of these will not extend the “interoperable subset” depicted in Figure 2 to completely envelop CPF and IEEE-1801: there are additional capabilities in each specification that maybe don’t need to be part of a mainstream converged methodology. Conversely, the degree of interoperability necessary to enable a converged methodology complete enough to meet the industry’s needs may be a work-in-process.

Avoid the use of incompatible UPF 1.0 constructs and methods

Examples of constructs that have better alternatives in IEEE 1801 are summarized in Table 1.

Table 1: UPF 1.0 constructs and their preferred IEEE 1801 and CPF alternatives

Table 1 highlights three methodology differences between UPF 1.0 and the new 1801 constructs. First, UPF 1.0 power intent specification is power and ground net–centric while 1801 is supply set–centric. The 1801 methodology is more flexible and complete. At the RTL design stage, designers typically do not have visibility into how the power and ground network will be implemented, and they may not even know the names of the supply nets. Using the supply set concept, the RTL designers can comfortably describe the virtual power network without even mentioning the names of the supply nets, which can be updated at the physical implementation stage. Furthermore, the state of a transistor is not determined by just power and ground nets―it also depends on other supply nets such as nwell or pwell supply. Therefore, simple power and ground net–based specification cannot describe the complete power intent.

The second difference is that 1801 supports the “successive refinement” methodology. What this means is that at different stages of a design flow, designers can choose to describe only the details of power intent needed for that design stage. This approach not only simplifies power intent specification at an early design stage, but also increases flexibility to refine power intent during later design stages. (For example, when supply nets are needed during the physical implementation stage, designers can use the associate_supply_set command to bind various supply nets to a supply set.) And the third difference: the new 1801 command add_power_state provides a more flexible and easier way to specify power states of a design that is consistent with the supply set concept. The old UPF 1.0 way, to specify power states in the Power State Table using the state of supply nets, requires the list of all supply nets of the current design scope. The new 1801 construct does not have this limitation; it has the additional capability to use Boolean function to describe any complex condition of a state as well as support hierarchical specification of power states.

Extend IEEE 1801 to include useful, commonly used CPF features

In 2011, the Si2 contributed the Open Low-Power Methodology (OpenLPM), which consists of a set of unique CPF features that are currently not available in IEEE 1801. Recent developments are progressing further: Si2 has recently worked with the IEEE to contribute all of CPF to further reduce the barriers to collaboration on methodology convergence. One such feature is the formal hierarchical design approach, including macro modeling for hardened intellectual property (IP). In a hierarchical design methodology, there is a need to load a block-level power intent file into a top-level power intent file to facilitate power intent creation. The command create_composite_domain in 1801 can be used to integrate power domains originated from different UPF files targeted for different blocks of a design.

With the OpenLPM contribution from Si2, the hierarchical flow of 1801 can be improved in the following ways:

• How to integrate the block-level power states at the top-level given the domain composition and top-level power state specifications
• How to integrate hard IP modeled using Liberty files (or power macro models) with blocks using domain composition; extend the semantics to enable domain composition on switchable sub-domains controlled by the same power gating–enable signal
• Clarify the prerequisites of domain composition to enable more automatic checks. For example, two sub-domains PD1 and PD2 may have illegal power states defined at the block level. After domain composition, each domain becomes a sub-domain of some top-level composite domain. But the two composite domains may have power states conflicting with the power states of PD1 and PD2. If such a scenario is defined as an error, tools can detect the illegal domain composition in the first place.

Nowadays, more and more custom IP blocks are created with power management features. Traditionally, modeling a custom IP block uses Liberty format. Even though Liberty is good enough to model some very basic low-power standard cells, it has limitations to model complex hard IP with advanced low-power techniques built in, such as:

• Input pin with diode protections
• Feedthrough and floating pins
• Supply set definition (required for hierarchical flow – composite domains)
• Voltage tolerance at input pins
• Regulated supplies, i.e. LDO
• Power states based on the supply sets of the IP

The required power-up sequence if there are multiple supplies that can be turned offAlthough Liberty could be extended to support some of these features, it is desirable to incorporate the power intent semantics related to all design entities into a single standard format, such as 1801. In addition, some of the information is clearly outside Liberty’s scope, such as the power states and state transitions or power-up sequence.

CPF has a formal approach to address hierarchical design. It has separate constructs for soft IP and hard IP. For low-power hard custom IP, the concept of the macro model is introduced with constructs to support all low-power features mentioned above. In addition to the hierarchical constructs, the OpenLPM highlighted many other CPF constructs that can benefit 1801. A subset of the constructs contributed by Si2 is summarized in Table 2.

 

Table 2: CPF constructs contributed to IEEE 1801 as part of the OpenLPM

 

Extend CPF to include useful, commonly used IEEE 1801 features

The third component required for methodology convergence, to extend CPF with useful features from 1801 that CPF was missing, has already occurred. Many of the extensions made to CPF 2.0 (the specification released by Si2 in February 2011) were to improve interoperability with IEEE 1801. These additions are summarized in Table 3 below.

 

Table 3: New CPF 2.0 constructs to increase interoperability with IEEE 1801

Conclusion

ARM, Cadence, Qualcomm, and Texas Instruments are working together with other members of the IEEE 1801 Working Group to facilitate this methodology convergence effort. The effort is already gaining wide industry support and will benefit all EDA suppliers, IP providers, and semiconductor companies as it eliminates redundant investment in multiple and conflicting methodologies and formats. There is still much work to do, but we believe we can see the light at the end of the tunnel―and it’s not an oncoming train.

References

IEEE 1801-2009 specification: http://www.techstreet.com/standards/ieee/1801_2009?product_id=1744966
Si2 CPF specification version 2.0: http://www.si2.org/cgi-bin/openeda.si2.org/download?group_id=51&file_id=1626&filename=si2_cpf_v2.0_14-feb-2011_with_Errata_14-mar-2011.pdf
Si2 Interoperability Guide: http://www.si2.org/?page=1126
Si2 press release: http://www.businesswire.com/news/home/20110531006613/en/Open-Low-Power-Methodology-Ushers-Era-Power-Interoperability

Article Courtesy: EDA DesignLine

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