What! How big did you say that FPGA is? (Team-design for FPGAs)

by Jeff Garrison, Synopsys , TechOnline India - September 28, 2010

Larger design teams, often geographically dispersed, are becoming much more common in the FPGA world. This trend has a significant impact on the tools used to design, verify and manage these increasingly complex electronic devices. This article describes a few of the key issues that should be considered when tackling complex FPGA design among several different engineers or teams of engineers.

Field-programmable gate arrays (FPGAs) have become incredibly capable with respect to handling large amounts of logic, memory, digital-signal-processor (DSP), fast I/O, and a plethora of other intellectual property (IP).

At 28-nm, FPGAs deliver the equivalent of a 20- to 30-million gate application-specific integrated circuit (ASIC). At this size, FPGA design tools, which have traditionally been used by just one or two engineers on a project, begin to break down. It is no longer practical for a single engineer, or even a very small design team, to design and verify these devices in a reasonable amount of time.

Of course, project schedules are always too long from a manager’s perspective and always too short from a design and verification engineer’s perspective. As a result, larger design teams, often geographically dispersed, are becoming much more common in the FPGA world. This trend has a significant impact on the tools used to design, verify and manage these increasingly complex electronic devices. This article describes a few of the key issues that should be considered when tackling complex FPGA design among several different engineers or teams of engineers.

There are many things to consider with regard to team-design, so it’s helpful to break it down into three key areas and discuss each separately as follows:

To read the full article, click here.

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