Multitest’s UltraFlat process meets needs of high parallel vertical probe card applications

by K C Krishnadas, TechOnline India - January 06, 2012

With the new process, the company is typically is able to comply with bow/twist requirements of 1.0 percent.

Germany's Multitest elektronische Systeme GmbH, a designer and manufacturer of final test handlers, contactors and load boards used by integrated device manufacturers (IDMs) and final test subcontractors worldwide, has said that its UtraFlat process meets the requirements of high parallel vertical probe card applications.

For applications such as DDR3 memory, the need for the flatness of boards at wafer level testing become crucial. For optimizing MLO/MLC attachments and contact element interfaces, a better surface is needed. Also, flatter PCBs require less compliance from the probe interface and reduce interface wear.

Leveraging the knowledge of PCB stack up engineering and PCB construction, Multitest developed the new 'UltraFlat' process to meet these requirements and this process makes for a very tight overall flatness tolerance to be maintained by removing the bow/twist in the PCB. Unlike "flat-baking" that provides a temporarily flat PCB, Mutltitest’s process provides a permanent overall flatness for the PCB.
 
With UltraFlat, Multitest typically is able to comply with bow/twist requirements of 1.0 percent.
 
For more information, please visit www.multitest.com/pcb.

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