Examining the case for analog automation

by Vanessa Knivett , TechOnline India - June 22, 2009

Complete automation of the analog IC design flow is a concept that has been debated for decades.

Complete automation of the analog IC design flow is a concept that has been debated for decades. With total automation still a distant goal, the EDA community has focused on automating elements of the design process, such as placement, circuit optimization, routing and verification.

But why does 100 percent automation evade us still--and, indeed, should it even be the focus?

"It's a worthy goal, a bit like trying to put people on Mars: I don't know whether we'll ever get there, but a lot of good technology gets derived from that," said Randolph Fish, director of marketing, custom layout and routing at Cadence Design Systems Inc.

An op amp layout is automatically placed using Modgens and Analog Placer.

Designing chips on a lighted drafting table/font>

"I love tools and love to automate," said Chris Collins, Texas Instruments' analog EDA manager. "But I don't believe in analog synthesis, because analog isn't structured. There are behavioral languages and so forth, but you'll never have a usable form of analog synthesis, and I am not seeing a lot of effort put into this area by vendors anymore."

The skepticism about analog automation--or, more specifically, analog synthesis--is not that surprising when you consider that the annals of analog EDA history are littered with companies that tried to tackle the job and failed. Nowadays, EDA vendors talk more about productivity improvements than synthesis, and there has indeed been productivity success in the analog domain.

For example, demand from mid- to high-complexity analog and mixed-signal applications, where increases in transistor count and parasitics have driven up simulation time, has prompted companies such as Cadence and Gemini Design Automation to turn to multicore computing and multithreaded software techniques to improve simulation speed and accuracy.

But simulation is just one aspect of the analog design flow. One of the biggest bottlenecks is layout. "Many analog designers aren't able to get the whole chip together and start simulating until close to the time when the design must go out the door," said TI's Collins. "If there's a mistake, then it's back to layout."


The days of Mylar prints and colored pens may be long gone, but for some, the first stage in addressing the layout bottleneck is to move away from the manual layout flow.

According to Jack Wild, senior technical lead in Cadence's custom layout team, many designers and layout engineers work with some level of automation and concurrency; that is, the layout designer starts working while the design engineer continues to tune. Tools are key here, he said. "We have more of a link between the schematic world and the physical world now. For example, if an engineer puts new constraints on the schematic, these will be highlighted in the layout automatically, and vice versa. This saves time in engineering change orders and enables layout to be updated more quickly."

Customers fit into two distinct groups, said Dave Millman, vice president of marketing at analog automaton provider Ciranova (Santa Clara, Calif.). "There are the discrete analog companies that are primarily using the traditional methodology, and for many of them it is working just fine. They want more productivity and would like to cut costs, but layout isn't killing them. And then there's the entire SoC business, where layout is killing them."

A current mirror (symmetrical layout) is automatically created as a Modgen with constraints assigned from the Virtuoso Schematic Editor.

Companies integrating complex analog and mixed-signal devices on SoCs, said Ciranova CEO Eric Filseth, "are much more aligned with the way that digital is done. They want to reuse IP and to integrate functionality that they have already proven into a new chip."

Typically, such companies are working on sub-65-nanometer chips. "At the more advanced nodes, the design rules can be overwhelming," said Cadence's Fish. "If you look at 45-nm designs--and we have customers starting to work with 32 and 28 nm--the rules around simple things like vias are incredibly complex. The ability to hide some of these rules from the layout engineer is very important, whether that is through automatic routing--where Cadence is doing a lot of work--or through automatic design rule enforcement."

Bluetooth specialist CSR does mixed-signal SoC designs at sub-65-nm geometries. "In the older geometries such as 180, 130 and even 90 nm, you could get away with remembering most of the design rules," said Paul Egan, CSR's head of physical design. "But as we look at 65 nm and below, the rules have become more complex and interdependent, and are difficult to carry around in your head."

The context-specific nature of sub-65-nm design rules is particularly challenging, said Egan. "If you design a structure in one particular way, it may be design-rule-correct [DRC] clean and electrically correct in one instance, but used elsewhere, its neighbor will interfere with it."


Vendors such as Cadence and Ciranova are tackling this lack of repeatability by bringing digital techniques to the analog domain in the form of high-level constraints.

In Ciranova's Helix tool, Millman said, such constraints were born from a desire to replicate circuit and layout designers' "mirror these, match those" conversations. A priority was to "automate the grunt work, leaving the judgment to the circuit and layout designer." Helix generates multiple DRC-clean layouts from which the layout designer can choose.

One driver for a constraint-driven approach is intellectual property reuse, said Cadence's Wild. "When we talk about constraints, in a reuse situation these parameters don't have to be reset and so can be used over."

A differential net pair is routed, with the flight lines to the target pins shown. The net names x and y are also shown.

But Fish added a caveat: "One of the biggest problems with reuse is that customers are in such a hurry that they are willing to throw out everything to get the current project done. If someone down the hall wants to use the block in another implementation, then you need to maintain that discipline of having the constraints centered, or having the connectivity maintained between the schematic and layout."

Though Fish is seeing more discipline in this area, Cadence's Virtuoso ADE 6.1 adds Circuit Prospector, which identifies standard topologies in the schematic, such as current mirrors. That pattern recognition capability finds regular occurrences and automatically applies constraints.

The constraint-driven approach only goes so far. As TI's Collins put it: "If you are working with non-high-performance analog, tools can help you take that IP and port it, but you'll still have to lay it out. In precision analog, even if you use complex device generators from node to node, the layout will have to be regenerated and re-handcrafted, and the corners of capacitors reshaved, to get a perfect-resolution ADC."


One untapped area of analog layout automation is routing, said CSR's Egan. "I have heard people say it is a simple step to add a router to a placement tool, but I don't agree. There's a huge difference between having a placement that you like and a finished layout. It is yet to be addressed in a repeatable way."

Millman said Ciranova is close to releasing a trial router. "An analog router needs to do an awful lot of things that we are not prepared to claim we can do," he said, but "this does a rapid job of trial routing to enable you to get a fast parasitic estimate."

Cadence plans a trial router by late 2009 that will work with the Helix placement tool. The 2009.06 release of Synopsys' Galaxy Custom Designer will have a multinet/bus router. Synopsys is working on a full device-level router, said Graham Etchells, director of marketing for Synopsys' analog/mixed signal group.

Here, devices are shown being automatically generated based on the schematic parameters and then placed in the same relative positions as in the schematic. Flight lines are visible between the connection points.

Whether the focus is constraint-driven layout methodology, automatic placement or trial routing, what is clear is that analog engineers are not resistant to automation. Indeed, far from it, said Collins: "If you can automate something and do it as well as I can, or better, then we'll use it."

What's needed, Egan said, are "reliable, predictable, repeatable design processes."

We're not there yet, but we're close.

Vanessa Knivett is editor of Analog DesignLine Europe.

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