Control issues: How FPGAs can address MCUs' general-purpose I/O scaling wall

by Mike Brogley, Actel Corp. , TechOnline India - September 09, 2009

The general-purpose inputs and outputs ports available for a microcontroller are usually limited in number. FPGAs can be deployed to overcome this barrier by adding four 8-bit ports to any 8-bit microcontroller. This article describes how to deploy an 8051-based FPGA as an 8-bit microcontroller.

Microcontrollers, in many ways, are the indispensable engines of our world. With hundreds of billions of them in use, MCUs play a variety of different but equally important roles in almost every electronics application imaginable. Inexpensive, easy to use and well understood, MCUs are an integral part of a design engineer's toolkit—and she can choose from thousands of controllers and controller variations.

But controllers do run into limits. The general-purpose input and output (GPIO) ports available for a microcontroller are usually limited in number. Many applications require more ports than are available on the microcontroller. And because GPIOs are used for a number of functions like serving as a gateway to numerous peripherals and buses, managing LEDs and interrupt sources, oftentimes more is better.

FPGAs, however, can be deployed to overcome this barrier by adding four 8-bit ports to any 8-bit microcontroller. With the broad IP libraries available from FPGA vendors today, it's a relatively straightforward endeavor. Take the 8051s soft microcontroller core. It can be configured as an 8-bit microcontroller, without sacrificing power budget, cost or board real estate.

The 8051s: History, Compatibility
Core8051s is an ASM51-compatible microcontroller core that can run programs written for the 8051. It contains the main 8051 core logic but no peripheral logic. Core8051s has an APB bus interface that can be used like the SFR bus to easily expand the functionality of the core by connecting it to existing APB IP peripherals. This allows users to configure the core with the peripheral functions, such as I/O ports that they need for their application.

It also features a high-performance 8-bit microcontroller, one clock per instruction and can be used with existing 8051 tools and code, among other things. {pagebreak}Configuration
The direction of each port can be configured as input or output on the fly . The microcontroller bus is compatible with CoreAPB3 (AMBA bus), and is tested and verified with an Actel ProASIC 3 device.

This design block can be used as a memory-mapped device of the 8051s embedded processor. The base address of this core is created during the processor configuration with Actel's SmartDesign tool. An active high chip select enables the block and several registers within the core are assigned offset addresses.

The design has four ports: PORT_A, PORT_B, PORT_C, and PORT_D. Each of these ports can be configured as either an input or output 8-bit port. For writing or reading data from any port, the direction (input or output) bit of the direction control register must be configured.


Click on image to enlarge.

To perform a write operation to any of these ports, first set the direction as output for the port, address the corresponding port and then write the data (data are written to the corresponding port output register.) When the WR signal is asserted, the output registers of that particular port are enabled. The content of the WRITE_DATA bus will be written to the output data register of the selected port on the rising edge of clock. The content of WRITE_DATA will remain at the port until the port content is overwritten.

For reading data from any port, set the direction of that port as input and load the address bus with the address of that port. Data will be transferred when RD is asserted for the READ_DATA bus and the controller will read the data. {pagebreak}Software and Test
The application software is written in C language. The program must be initially downloaded to the program memory of the 8051s. The offset address corresponding to the various registers is hardcoded.

When a write cycle has to be performed, the direction control bit is initially set, followed by a write to that port. For a read cycle, the corresponding direction control bit is set and a read is performed from that port.

Actel's SoftConsole v2.1 is used for the software development and the FS2' ISA-Actel51 console is used for executing the program.

The on-board switches are connected to one of the input ports (PORT_D) and the nLEDs on the board are connected to one of the output ports (PORT_C). The software program continuously reads from the input port and sends data to the output port. Whenever the switch positions are changed, the LED indications also change correspondingly.

This design can be used in microcontroller-based setups where the number of ports needed exceeds the number of ports available on a microcontroller integrated circuit. This design requires minimal FPGA resources and can be accommodated by most of Actel's IGLOO' and ProASIC3 FPGAs. Even though the design mentioned in this example is for four 8-bit ports, the code can be easily modified to add additional ports or change the width of the ports.

About the Author
Mike Brogley, IP and Solutions Product Marketing Manager, joined Actel in 2005, bringing 20 years of experience in the technology industry. Prior to joining the company, he spent more than 15 years at LSI Logic Corp., where he held a variety of technical, operational and management roles. Brogley holds a bachelor's degree in aeronautics from San Jose State University. He is a member of IEEE, AIAA and SAE and is a life member of AFCEA and USNI.

Comments

blog comments powered by Disqus