Hunting that elusive bug

by Roland Syba, Melexis GmbH , TechOnline India - September 29, 2010

This article discusses the non-trivial challenge of detecting and correcting the – often elusive – functional defects that unavoidably arise in the design of complex system-on-chip (SoC) devices. How do we mitigate the conflict between the dramatic increase in SoC design complexity and the need to deliver the design in a shorter time with the same or better design quality?

This article discusses the non-trivial challenge of detecting and correcting the – often elusive – functional defects that unavoidably arise in the design of complex system-on-chip (SoC) devices. How do we mitigate the conflict between the dramatic increase in SoC design complexity and the need to deliver the design in a shorter time with the same or better design quality?

Clearly, we need new design and verification methods, and we need “all hands on deck” to develop them. That’s why a consortium of six companies and six research institutes set up the Herkules project [1], with support from the German government. Over the past three years, this project teamed design and verification engineers from leading chip companies and developers of commercial verification tools from EDA companies, together with leading technology research institutes. Their goal was to develop a right-first-time verification approach for large digital and mixed-signal designs – and to ensure that it is widely applicable to the development of automotive and telecommunication systems that must comply with very high quality standards.

And why is Melexis interested in these verification issues? We develop and produce a broad range of mixed-signal, high voltage ASICs and ASSP for automotive applications, increasingly equipped with integrated flash and microcontroller(s), local interconnect network (LIN) physical layer or complete LIN controller, and controller area network (CAN) components. In common with most providers of complex SoCs, we implement a re-usable intellectual property (IP) methodology to speed time to market and reduce development costs.

To read the full article, click here.

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