A puddle of gates

October 28, 2011

Sometimes a puddle of gates makes a lot more sense than a sea of gates.

 

The holy grail of PR people is to get some reference to their latest widget in print, or at least in webized bits. So at every Embedded Systems Conference my schedule is packed with meetings with vendors touting their latest wares. The stories are usually pretty interesting, but only a handful seem important enough to mention here.

Altera has an answer to Xilinx’s Zynq Cortex-A9 cum FPGA fabric parts: a Cortex-A9 with FPGA fabric. In both cases these parts offer fabulous computing power with gobs of configurable logic. (Both companies offer other CPUs and configurations as well). These parts twist the FPGA paradigm a bit by their focus on combining a high-end processor with plenty of standard I/O, and a decent, but not extreme, number of FPGA logic cells.

In the olden days programmable logic meant PALs, which had a minimal number of logic cells. FPGAs arrived and soon offered what became known as a “sea of gates;” a huge number of configurable logic components. So many, in fact, that the vendors offered IP with which one could implement multiple CPUs on an FPGA.

At the ESC Microchip made a fascinating announcement: they are taking the idea of combining a microcontroller with configurable logic to a new low. Instead of a sizzling 32 bitter with hundreds of thousands of configurable cells, the PIC10F32X and PIC1XF150X family includes 8 bit CPUs, a bit of memory (up to 14KB flash and up to 512 bytes of RAM), some I/O, and up to 4 “configurable logic cells,” or CLCs.

Each CLC comprises, first, four multiplexers that let you select, under software control, four of 8 signal sources. These include PWM outputs, I/O pins, and other components on the device. The four selected signals are routed to logic components that can perform various Boolean and latching functions. The output of that drives either output pins or triggers an interrupt. All sorts of polarity inversion can be performed at the different stages.

Bottom line: compared to a modern FPGA the CLC functionality is sort of minimal. As Microchip’s Eric Lawson said: “Instead of a sea of gates, we have a puddle of gates.”

Instead of a package with hundreds of pins, these parts use 6 to 20.

Instead of requiring hefty power supplies, these parts consume 20 nA in sleep mode and under 30 uA/MHz while active.

Instead of a fairly complex configuration scheme, the CLCs are set up by the code at run time. The logic design can change on-the-fly.

Less is often more.

The original PIC parts were often used as PAL replacements, as a little bit of software could do a whole lot more than a rather constrained PAL. But software is slow. By coupling a puddle of gates to a processor one can get the best of both hardware and software, and a mix of the two.

8 bit processors don’t have a lot of sex appeal, and always lose in the PR battle to datasheets that scream about megagigaweenieHertz or new cache coherency schemes. But an awful lot of products either don’t need, or can’t afford, a hyped-up ride.

Microchip’s low-end parts are more like the family sedan: they take care of the unglamorous but hugely essential tasks that keep the world running.

 

Jack G. Ganssle is a lecturer and consultant on embedded development issues. He conducts seminars on embedded systems and helps companies with their embedded challenges. Contact him at jack@ganssle.com. His website is www.ganssle.com.

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